Chapter32 fcc transparent controller, Chapter 32, Fcc transparent controller – Motorola MPC8260 User Manual

Page 921: Chapter 32, òfcc transparent controller, Chapter 32 fcc transparent controller

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MOTOROLA

Chapter 32. FCC Transparent Controller

32-1

Chapter 32
FCC Transparent Controller

320

320

The FCC transparent controller functions as a high-speed serial-to-parallel and parallel-to-
serial converter. Transparent mode provides a clear channel on which the FCC performs no
bit-level manipulationÑimplementing higher-level protocols would require software.
Transparent mode is also referred to as a totally transparent or promiscuous operation.

Basic applications for an FCC in transparent mode include the following:

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For data, such as voice, moving serially without the need for protocol processing

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For board-level applications, such as chip-to-chip communications, requiring a
serial-to-parallel and parallel-to-serial conversion

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For applications requiring the switching of data paths without altering the protocol
encoding itself, such as a multiplexer in which data from a high-speed TDM serial
stream is divided into multiple low-speed data streams

An FCC transmitter and receiver can be programmed in transparent mode independently.
Setting GFMRx[TTx] enables the transparent transmitter; setting GFMRx[TRx] enables
the transparent receiver. Both bits must be set for full-duplex transparent operation. If only
one bit is set, the other half of the FCC operates with the protocol programmed in
GFMRx[MODE]. This allows loopback modes to transfer data from one memory location
to another (using DMA) while the data is converted to a speciÞc serial format. However,
the Ethernet and ATM controllers cannot be split in this way. See Section 28.2, ÒGeneral
FCC Mode Registers (GFMRx).
Ó

The FCC in transparent mode can work with the TSA or NMSI and support modem lines
using the general-purpose I/O signals. The data can be transmitted and received with msb
or lsb Þrst in each octet. The FCC consists of separate transmit and receive sections whose
operations are asynchronous with the core and can either be synchronous or asynchronous
with respect to the other FCCs. Each clock can be supplied from the internal BRG bank or
external signals.

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