Motorola MPC8260 - Manual (Page 475)

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-21
Part IV. Communications Processor Module
Figure 14-14 shows the effects of changing FE when CE = 1 with a 1-bit frame sync delay.
Figure 14-14. Falling Edge (FE) Effect When CE = 1 and xFSD = 01
Figure 14-15 shows the effects of changing FE when CE = 0 with a 1-bit frame sync delay.
Figure 14-15. Falling Edge (FE) Effect When CE = 0 and xFSD = 01
L1TxD
Rx Sampled Here
L1ST
L1SYNC
L1SYNC
L1CLK
(Bit-0)
(On Bit-0)
L1ST Driven from Clock High for Both FE Settings
xFSD=01
(FE=0)
(FE=1)
CE=1
L1TXD
Rx Sampled Here
L1ST
L1SYNC
L1SYNC
L1CLK
(Bit-0)
(On Bit-0)
L1ST is Driven from Clock Low
(FE=0)
(FE=1)
CE=0
in Both the FE Settings
xFSD=01