Motorola MPC8260 - Manual (Page 288)

10-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
10.2.13 Partial Data Valid Indication (PSDVAL)
The 60x and local buses have an internal 64-bit data bus. According to the 60x bus
speciÞcation, TA is asserted when up to a double word of data is transferred. Because the
MPC8260 supports memories with port sizes smaller than 64 bits, there is a need for partial
data valid indication. The memory controller uses PSDVAL to indicate that data is latched
by the memory on write accesses or valid data is present on read accesses. The quantity of
the data depends on the memory port size and the transfer size. The memory controller
accumulates PSDVAL assertions, and when a double word (or the transfer size) is
transferred, the memory controller asserts TA to indicate that a 60x data beat was
transferred. Table 10-1 shows the number of PSDVAL assertions needed for one TA
assertion under various circumstances.
Figure 10-5 shows a double-word transfer on 32-bit port size memory.
Table 10-1. Number of PSDVAL Assertions Needed for TA Assertion
Port Size Transfer Size PSDVAL Assertions TA Assertions
64 Any 1 1
32 Double word 2 1
32 Word/half word/byte (32-bit aligned) 1 1
16 Double Word 4 1
16 Word 2 1
16 Half/byte 1 1
8 Double word 8 1
8 Word 4 1
8 Half 2 1
8 Byte 1 1