Motorola MPC8260 - Manual (Page 482)

14-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
The basic rate IDL bus has the three following channels:
¥ B1 is a 64-Kbps bearer channel
¥ B2 is a 64-Kbps bearer channel
¥ D is a 16-Kbps signaling channel
There are two deÞnitions of the IDL bus frame structureÑ8 and 10 bits. The only difference
between them is the channel order within the frame. See Figure 14-23.
Figure 14-23. IDL Bus Signals
Note that previous versions of Motorola IDL-deÞned bit functions called auxiliary (A) and
maintenance (M) were removed from the IDL deÞnition when it was concluded that the
IDL control channel would be out-of-band. These functions were deÞned as a subset of the
Motorola SPI format called serial control port (SCP). To implement the A and M bits as
originally deÞned, program the TSA to access these bits and route them transparently to an
SCC or SMC. Use the SPI to perform out-of-band signaling.
The MPC8260 supports all channels of the IDL bus in the basic rate. Each bit in the IDL
frame can be routed to any SCC and SMC or can assert a strobe output for supporting an
external device. The MPC8260 supports the request-grant method for contention detection
on the D channel of the IDL basic rate and when the MPC8260 has data to transmit on the
D channel, it asserts L1RQx. The physical layer device monitors the physical layer bus for
activity on the D channel and indicates that the channel is free by asserting L1GRx. The
MPC8260 samples the L1GRx signal when the IDL sync signal (L1RSYNCx) is asserted.
If L1GRx is asserted, the MPC8260 sends the Þrst zero of the opening ßag in the Þrst bit
L1CLK
L1SYNC
L1RXD
L1TXD
B1 D1
10-Bit IDL
D2
B1 D1 B2 D2
L1RXD
L1TXD
B1 D1
8-Bit IDL
D2
B1 B2 D2
B2
D1
B2
Notes:
1. Clocks are not to scale.
2. L1RQx and L1GRx are not shown.