Motorola MPC8260 - Manual (Page 143)

MOTOROLA Chapter 4. System Interface Unit (SIU) 4-5
Part II. ConÞguration and Reset
Figure 4-4. TMCNT Block Diagram
Section 4.3.2.15, ÒTime Counter Register (TMCNT),Ó describes the time counter register.
4.1.4 Periodic Interrupt Timer (PIT)
The periodic interrupt timer consists of a 16-bit counter clocked by timersclk. The 16-bit
counter decrements to zero when loaded with a value from the periodic interrupt timer
count register (PITC); after the timer reaches zero, PISCR[PS] is set and an interrupt is
generated if PISCR[PIE] = 1. At the next input clock edge, the value in the PITC is loaded
into the counter and the process repeats. When a new value is loaded into the PITC, the PIT
is updated, the divider is reset, and the counter begins counting.
Setting PS creates a pending interrupt that remains pending until PS is cleared. If PS is set
again before being cleared, the interrupt remains pending until PS is cleared. Any write to
the PITC stops the current countdown and the count resumes with the new value in PITC.
If PTE = 0, the PIT cannot count and retains the old count value. The PIT is not affected by
reads. Figure 4-5 is a block diagram of the PIT.
Figure 4-5. PIT Block Diagram
Divide
32-Bit Counter
32-Bit Register
SEC
Alarm
=
Interrupt
Interrupt
by 8,192
timersclk for TMCNT (8,192 Hz)
Clock
PITC
timersclk
PISCR[PS]
PISCR[PIE]
PIT
PISCR[PTE]
Disable for PIT
16-Bit Modulus
Interrupt
Counter