Motorola MPC8260 - Manual (Page 260)

8-28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
¥ Asserting ARTRY causes the data tenure to be terminated immediately if the
ARTRY is for the address tenure associated with the data tenure in operation (the
data tenure may not be terminated due to address pipelining). The earliest allowable
assertion of TA depends directly on the latest possible assertion of ARTRY.
Figure 8-8 shows both a single-beat and burst data transfer. The MPC8260 asserts TA to
mark the cycle in which data is accepted. In a normal burst transfer, the fourth assertion of
TA signals the end of a transfer.
Figure 8-8. Single-Beat and Burst Data Transfers
8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration
The MPC8260 allows an address tenure to overlap its associated data tenure. The MPC8260
internally guarantees that the Þrst TA of the data tenure is delayed to be at the same time or
after the ARTRY window (the clock after the assertion of AACK).
8.5.5 Port Size Data Bus Transfers and PSDVAL Termination
The MPC8260 can transfer data via data ports of 8, 16, 32, and 64 bits, as shown in
Section 8.4.3, ÒAddress Transfer Attribute Signals.Ó Single-beat transaction sizes can be 8,
16, 32, 64, 128, and 192 bits; burst transactions are 256 bits. Single-beat and burst
transactions are divided into to a number of intermediate beats depending on the port size.
The MPC8260 asserts PSDVAL to mark the cycle in which data is accepted. Assertion of
PSDVAL in conjunction with TA marks the end of the transfer in single-beat mode. The
fourth assertion of PSDVAL in conjunction with TA signals the end of a burst transfer.
CLKOUT
ADDR + ATTR
TS
AACK
DBG
TA
D[0Ð63]
PSDVAL
D0 D1 D2 D3