Motorola MPC8260 - Manual (Page 996)

Index-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
INDEX
TxBD, 26-33
serial peripheral interface (SPI)
SPCOM, 33-9
SPIE, 33-9
SPIM, 33-9
SPMODE, 33-6
system interface unit (SIU)
BCR, 4-25
IMMR, 4-34
L_TESCR1, 4-38
L_TESCR2, 4-39
LCL_ACR, 4-29
LCL_ALRH, 4-30
LCL_ALRL, 4-30
PISCR, 4-42
PITC, 4-43
PITR, 4-44
PPC_ACR, 4-28
PPC_ALRH, 4-28
PPC_ALRL, 4-29
SCPRR_H, 4-19
SCPRR_L, 4-20
SICR, 4-17
SIEXR, 4-24
SIMR_H, 4-22
SIMR_L, 4-22
SIPNR_H, 4-21
SIPNR_L, 4-21
SIPRR, 4-18
SIUMCR, 4-31
SIVEC, 4-23
SWR, 4-7
SWSR, 4-36
SYPCR, 4-35
TESCR1, 4-36
TESCR2, 4-37
TMCNT, 4-41
TMCNTAL, 4-41
TMCNTSC, 4-40
TFCR, 19-15
timers
TCN, 17-8
TCR, 17-8
TER, 17-8
TGCR, 17-4
TMR, 17-6
TRR, 17-7
TODR
AppleTalk mode, 25-4
overview, 19-9
TOSEQ, 20-10
transparent mode
PSMR, 23-9
SCCE, 23-12
SCCM, 23-12
SCCS, 23-13
UART mode
DSR, 20-11
PSMR, 20-13
SCCE, 20-19
SCCM, 20-19
SCCS, 20-21
TOSEQ, 20-10
Reset
actions, 5-2
causes, 5-1
external HRESET flow, 5-3
external SRESET flow, 5-3
power-on reset flow, 5-2
receiver reset sequence, SCC, 19-27
resetting registers and parameters for all
channels, 13-11
software watchdog reset, 5-1
transmitter reset sequence, SCC, 19-27
RFCR (Rx buffer function code register)
overview, 19-15
RISC microcontroller, seeCommunications
processor (CP)
RISC timer tables
CP loading tracking, 13-24
features list, 13-19
initializing RISC timer tables, 13-22
interrupt handling, 13-23
overview, 13-18
parameter RAM, 13-19
pulse width modulation (PWM) channels, 13-19
RAM usage, 13-19
RTER, 13-21
RTMR, 13-21
scan algorithm, 13-23
SET TIMER command, 13-22
table entries, 13-21
timer counts, comparing, 13-24
TM_CMD, 13-20
tracking CP loading, 13-24
RMR (reset mode) register, 5-5
RSR (reset status) register, 5-4
RSTATE (internal receiver state) register, 27-11
RTER (RISC timer event register), 13-21
RTMR (RISC timer mask register), 13-21
RTSCR (RISC time-stamp control register), 13-9
RTSR (RISC time-stamp register), 13-10
S
SCC memory map, 3-9
SCCE (SCC event) register
BISYNC mode, 22-15
HDLC mode, 21-12