Motorola MPC8260 - Manual (Page 562)

19-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Figure 19-3 shows GSMR_L.
Table 19-2 describes GSMR_L Þelds.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ EDGE TCI TSNC RINV TINV TPL TPP TEND TDCR
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11A00 (SCC1); 0x11A20 (SCC2); 0x11A40 (SCC3); 0x11A60 (SCC4)
Bit 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field RDCR RENC TENC DIAG ENR ENT MODE
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11A02 (SCC1); 0x11A22 (SCC2); 0x11A42 (SCC3); 0x11A62 (SCC4)
Figure 19-3. GSMR_LÑGeneral SCC Mode Register (Low Order)
Table 19-2. GSMR_L Field Descriptions
Bit Name Description
0 Ñ Reserved, should be cleared.
1Ð2 EDGE Clock edge. Determines the clock edge the DPLL uses to adjust the receive sample point due to jitter
in the received signal. Ignored in UART protocol or if the 1x clock mode is selected in RDCR.
00 Both the positive and negative edges are used for changing the sample point (default).
01 Positive edge. Only the positive edge of the received signal is used to change the sample point.
10 Negative edge. Only the negative edge of the received signal is used to change the sample point.
11 No adjustment is made to the sample point.
3 TCI Transmit clock invert.
0 Normal operation.
1 Before it is used, the internal Tx clock (TCLK) is inverted by the SCC so it can clock data out one-
half clock earlier (on the rising rather than the falling edge). In this case, the SCC offers a minimum
and maximum rising clock edge-to-data speciÞcation. Data output by the SCC after the rising edge
of an external Tx clock can be latched by the external receiver one clock cycle later on the next
rising edge of the same Tx clock. Recommended for Ethernet, HDLC, and transparent operation
when clock rates exceed 8 MHz to improve data setup time for the external transceiver.
4Ð5 TSNC Transmit sense. Determines the amount of time the internal carrier sense signal stays active after the
last transition on RXD, indicating that the line is free. For instance, AppleTalk can use TSNC to avoid
a spurious CS-changed (SCCE[DCC]) interrupt that would otherwise occur during the frame sync
sequence before the opening ßags. If RDCR is conÞgured to 1
´ clock mode, the delay is the greater
of the two numbers listed. If RDCR is conÞgured to 8 ´, 16´, or 32´ mode, the delay is the smaller
number.
00 InÞnite. Carrier sense is always active (default).
01 14- or 6.5-bit times as determined by RDCR.
10 4- or 1.5-bit times as determined by RDCR (normally for AppleTalk).
11 3- or 1-bit times as determined by RDCR.
6 RINV DPLL Rx input invert data. Must be zero in HDLC bus mode or asynchronous UART mode.
0 Do not invert.
1 Invert data before sending it to the DPLL for reception. Used to produce FM1 from FM0 and NRZI
space from NRZI mark or to invert the data stream in regular NRZ mode.