Motorola MPC8260 - Manual (Page 320)

10-44 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Figure 10-31. SDRAM Four-Beat Burst Read, Page Miss, CL = 3
Figure 10-32. SDRAM Single-Beat Write, Page Hit
Figure 10-33. SDRAM Three-Beat Burst Write, Page Closed
CLK
ALE
CS
SDRAS
SDCAS
MA[0Ð11]
WE
DQM
Data D0
Z A10 = 1
BS *
* BSÑBank select according to SDRAM organization. A10 = 1 means not all banks will be precharged.
Row
CAS Latency = 3
Col
D1 D2 D4
Deactivate Activate
CLK
ALE
CS
SDRAS
SDCAS
MA[0Ð11] Column
WE
DQM
Data D0
CLK
ALE
CS
SDRAS
SDCAS
MA[0Ð11] Row Column
WE
DQM
Data D0 D1 D2