Motorola MPC8260 - Manual (Page 773)

MOTOROLA Chapter 28. Fast Communications Controllers (FCCs) 28-15
Part IV. Communications Processor Module
6. Write the FDSR.
7. Initialize the required values for this FCC in its parameter RAM.
8. Clear out any current events in FCCE, as needed.
9. Write the FCCM register to enable the interrupts in the FCCE register.
10. Write the SCPRR_H to conÞgure the FCC interrupt priority.
11. Clear out any current interrupts in the SIPNR_L, if preferred.
12. Write the SIMR_L to enable interrupts to the CP interrupt controller.
13. Issue an INIT TX AND RX PARAMETERS command (with the correct protocol number).
14. Set GFMR[ENT] and GFMR[ENR].
The Þrst RxBDÕs empty bit must be set before the INIT RX COMMAND . However TxBDs can
have their ready bits set at any time. Notice that the CPCR does not need to be accessed
after a power-on reset until an FCC is to be used. An FCC should be disabled and reenabled
after any dynamic change in its parallel I/O ports or serial channel physical interface
conÞguration. A full reset using CPCR[RST] is a comprehensive reset that also can be used.
28.10 FCC Interrupt Handling
The following describes what usually occurs within an FCC interrupt handler:
1. When an interrupt occurs, read FCCE to determine interrupt sources. FCCE bits to
be handled in this interrupt handler are normally cleared at this time.
2. Process the TxBDs to reuse them if the FCCE[TX,TXE] were set. If the transmit
speed is fast or the interrupt delay is long, more than one transmit buffer may have
been sent by the FCC. Thus, it is important to check more than just one TxBD during
the interrupt handler. One common practice is to process all TxBDs in the interrupt
handler until one is found with R set.
3. Extract data from the RxBD if FCCE[RX, RXB, or RXF] is set. If the receive speed
is fast or the interrupt delay is long, the FCC may have received more than one
receive buffer. Thus, it is important to check more than just one RxBD during
interrupt handling. Typically, all RxBDs in the interrupt handler are processed until
one is found with E set. Because the FCC prefetches BDs, the BD table must be big
enough such that always there will be another empty BD to prefetch.
4. Clear FCCE.
5. Continue normal execution.
28.11 FCC Timing Control
When GFMR[DIAG] is programmed to normal operation, CD and CTS are automatically
controlled by the FCC. GFMR[TCI] is assumed to be cleared, which implies normal
transmit clock operation.