Motorola MPC8260 - Manual (Page 891)

MOTOROLA Chapter 30. Fast Ethernet Controller 30-17
Part IV. Communications Processor Module
In the physical type of address recognition, the Ethernet controller compares the destination
address Þeld of the received frame with the physical address that the user programs in the
PADDR. If it fails, the controller performs address recognition on multiple individual
addresses using the IADDR_H/L hash table. Since the controller always checks PADDR
and the individual hash, for individual address the user must write zeros to the hash in order
to avoid a hash match and ones to PADDR in order to avoid individual address match.
In the group type of address recognition, the Ethernet controller determines whether the
group address is a broadcast address. If it is a broadcast and broadcast addresses are
enabled, the frame is accepted. If the group address is not a broadcast address, the user can
perform address recognition on multiple group addresses using the GADDR_H/L hash
table. In promiscuous mode, the Ethernet controller receives all of the incoming frames
regardless of their address when an external CAM is not used.
If an external CAM is used for address recognition (FPSMR[CAM] = 1), the user should
select promiscuous mode; the frame can be rejected if there is no match in the CAM. If the
on-chip address recognition functions detect a match, the external CAM is not accessed.
30.13 Hash Table Algorithm
The hash table process used in the individual and group hash Þltering operates as follows.
The Ethernet controller maps any 48-bit address into one of 64 bins, which are represented
by the 64 bits in GADDR_H/L or IADDR_H/L. When the
SET GROUP ADDRESS command
is executed, the Ethernet controller maps the selected 48-bit address in TADDR into one of
the 64 bits. This is performed by passing the 48-bit address through the on-chip 32-bit CRC
generator and using 6 bits of the CRC-encoded result to generate a number between 1 and
64. Bit 26 of the CRC result selects between the two GADDRs or IADDRs; bits 27Ð31 of
the CRC result select which bit is set.
The same process is used when the Ethernet controller receives a frame. If the CRC
generator selects a bit that is set in the group/individual hash table, the frame is accepted;
otherwise, it is rejected. The result is that if eight group addresses are stored in the hash
table and random group addresses are received, the hash table prevents roughly 56/64
(87.5%) of the group address frames from reaching memory. The core must further Þlter
those that reach memory to determine if they contain one of the eight preferred addresses.
Better performance is achieved by using the group and individual hash tables in
combination. For instance, if eight group and eight physical addresses are stored in their
respective hash tables, 87.5% of all frames (not just group address frames) are prevented
from reaching memory.
The effectiveness of the hash table declines as the number of addresses increases. For
instance, with 128 addresses stored in a 64-bin hash table, the vast majority of the hash table
bits are set, preventing only a small fraction of frames from reaching memory. In such
instances, an external CAM is advised if the extra bus use cannot be tolerated. See
Section 30.7, ÒCAM Interface.У