Motorola MPC8260 - Manual (Page 349)

MOTOROLA Chapter 10. Memory Controller 10-73
Part III. The Hardware Interface
20 G5T1 General-purpose line 5 timing 1. DeÞnes the state of GPL5 during phase 1Ð2.
0 The value of the GPL5 line at the rising edge of T1 will be 0
1 The value of the GPL5 line at the rising edge of T1 will be 1
21 G5T3 General-purpose line 5 timing 3. DeÞnes the state of GPL5 during phase 3Ð4.
0 The value of the GPL5 line at the rising edge of T3 will be 0
1 The value of the GPL5 line at the rising edge of T3 will be 1
22Р23 С Redo current RAM word. See ÒSection 10.6.4.1.5, ÒRepeat Execution of Current RAM Word (REDO).Ó
00 Normal operation
01 The current RAM word is executed twice.
10 The current RAM word is executed tree times.
11 The current RAM word is executed four times.
24 LOOP Loop. The Þrst RAM word in the RAM array where LOOP is 1 is recognized as the loop start word.
The next RAM word where LOOP is 1 is the loop end word. RAM words between the start and end
are deÞned as the loop. The number of times the UPM executes this loop is deÞned in the
corresponding loop Þeld of the MxMR.
0 The current RAM word is not the loop start word or loop end word.
1 The current RAM word is the start or end of a loop.
See Section 10.6.4.1.4, ÒLoop Control.Ó
25 EXEN Exception enable. If an external device asserts TEA or RESET, EXEN allows branching to an
exception pattern at the exception start address (EXS) at a Þxed address in the RAM array.
When the MPC8260 under UPM control begins accessing a memory device, the external device may
assert TEA or SRESET. An exception occurs when one of these signals is asserted by an external
device and the MPC8260 begins closing the memory cycle transfer. When one of these exceptions is
recognized and EXEN in the RAM word is set, the UPM branches to the special exception start
address (EXS) and begins operating as the pattern deÞned there speciÞes. See Table 10-34. The
user should provide an exception pattern to deassert signals controlled by the UPM in a controlled
fashion. For DRAM control, a handler should negate RAS and CAS to prevent data corruption. If
EXEN = 0, exceptions are deferred and execution continues. After the UPM branches to the
exception start address, it continues reading until the LAST bit is set in the RAM word.
0 The UPM continues executing the remaining RAM words.
1 The current RAM word allows a branch to the exception pattern after the current cycle if an
exception condition is detected. The exception condition can be an external device asserting TEA
or SRESET.
26Ð27 AMX Address multiplexing. Determines the source of A[0Ð31] at the rising edge of t1 (single-MPC8260
mode only). See Section 10.6.4.2, ÒAddress Multiplexing.Ó
00 A[0Ð31] is the non-multiplexed address. For example, column address.
01 Reserved.
10 A[0Ð31] is the address requested by the internal master multiplexed according to MxMR[AMx].
For example, row address.
11 A[0Ð31] is the contents of MAR. Used for example, during SDRAM mode initialization.
28 NA Next address. Determines when the address is incremented during a burst access.
0 The address increment function is disabled
1 The address is incremented in the next cycle. In conjunction with the BRx[PS], the increment value
of A[27Ð31] and/or BADDR[27Ð31] at the rising edge of T1 is as follows
If the accessed bank has a 64-bit port size, the value is incremented by 8.
If the accessed bank has a 32-bit port size, the value is incremented by 4.
If the accessed bank has a 16-bit port size, the value is incremented by 2.
If the accessed bank has an 8-bit port size, the value is incremented by 1.
Note: The value of NA is relevant only when the UPM serves a burst-read or burst-write request. NA
is reserved under other patterns.
Table 10-35. RAM Word Bit Settings (Continued)
Bit Name Description