Motorola MPC8260 - Manual (Page 717)

MOTOROLA Chapter 26. Serial Management Controllers (SMCs) 26-21
Part IV. Communications Processor Module
However, the SMC in transparent mode provides a data character length option of 4 to 16
bits, whereas the SCCs provide 8 or 32 bits, depending on GSMR[RFW]. The SMC in
transparent mode is also referred to as the SMC transparent controller.
26.4.1 Features
The following list summarizes the features of the SMC in transparent mode:
¥ Flexible data buffers
¥ Connects to a TDM bus using the TSA in an SIx
¥ Transmits and receives transparently on its own set of signals using a sync signal to
synchronize the beginning of transmission and reception to an external event
¥ Programmable character length (4Ð16)
¥ Reverse data mode
¥ Continuous transmission and reception modes
¥ Four commands
26.4.2 SMC Transparent Channel Transmission Process
The transparent transmitter is designed to work with almost no core intervention. When the
core enables the SMC transmitter in transparent mode, it starts sending idles. The SMC
immediately polls the Þrst BD in the transmit channel BD table and once every character
time, depending on the character length (every 4 to 16 serial clocks). When there is a
message to transmit, the SMC fetches the data from memory and starts sending the message
when synchronization is achieved.
Synchronization can be achieved in two ways. First, when the transmitter is connected to a
TDM channel, it can be synchronized to a time slot. Once the frame sync is received, the
transmitter waits for the Þrst bit of its time slot before it starts transmitting. Data is sent only
during the time slots deÞned by the TSA. Secondly, when working with its own set of
signals, the transmitter starts sending when SMSYNx is asserted.
When a BD data is completely written to the transmit FIFO, the L bit is checked and if it is
set, the SMC writes the message status bits into the BD and clears the R bit. It then starts
transmitting idles. When the end of the current BD is reached and the L bit is not set, only
R is cleared. In both cases, an interrupt is issued according to the I bit in the BD. By
appropriately setting the I bit in each BD, interrupts can be generated after each buffer, a
speciÞc buffer, or each block is sent. The SMC then proceeds to the next BD. If no
additional buffers have been presented to the SMC for transmission and the L bit was
cleared, an underrun is detected and the SMC begins sending idles.
If the CM bit is set in the TxBD, the R bit is not cleared, so the CP can overwrite the buffer
on its next access. For instance, if a single TxBD is initialized with the CM and W bits set,
the buffer is sent continuously until R is cleared in the BD.