Motorola MPC8260 - Manual (Page 106)

2-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
Computational instructions do not modify memory. To use a memory operand in a
computation and then modify the same or another memory location, the memory contents
must be loaded into a register, modiÞed, and then written back to the target location with
separate instructions. Decoupling arithmetic instructions from memory accesses increases
throughput by facilitating pipelining.
PowerPC processors follow the program ßow when they are in the normal execution state.
However, the ßow of instructions can be interrupted directly by the execution of an
instruction or by an asynchronous event. Either kind of exception may cause one of several
components of the system software to be invoked.
2.3.2.3 MPC8260 Implementation-SpeciÞc Instruction Set
The MPC8260 processor core instruction set is deÞned as follows:
¥ The processor core provides hardware support for all 32-bit PowerPC instructions.
¥ The processor core provides two implementation-speciÞc instructions used for
software table search operations following TLB misses:
Ñ Load Data TLB Entry (tlbld)
Ñ Load Instruction TLB Entry (tlbli)
¥ The processor core implements the following instructions deÞned as optional by the
PowerPC architecture:
Ñ External Control In Word Indexed (eciwx)
Ñ External Control Out Word Indexed (ecowx)
Ñ Store Floating-Point as Integer Word Indexed (stÞwx)
The MPC8260 does not provide the hardware support for misaligned eciwx and
ecowx instructions provided by the MPC603e processor. An alignment exception is
taken if these instructions are not word-aligned.
2.4 Cache Implementation
The MPC8260 processor core has separate data and instruction caches. The cache
implementation is described in the following sections.
2.4.1 PowerPC Cache Model
The PowerPC architecture does not deÞne hardware aspects of cache implementations. For
example, some PowerPC processors, including the MPC8260Õs processor core, have
separate instruction and data caches (Harvard architecture), while others, such as the
PowerPC 601¨ microprocessor, implement a uniÞed cache.