Motorola MPC8260 - Manual (Page 873)

MOTOROLA Chapter 29. ATM Controller 29-93
Part IV. Communications Processor Module
For example, suppose a system uses a 155.52-Mbps OC-3 device as PHY0, but the
maximum required data rate is only 100 Mbps. In transmit internal rate mode, the user can
conÞgure the internal rate mechanism to clock the ATM transmitter at a cell rate of 100
Mbps. If the system clock is 133 MHz, program a BRG to divide the system clock by 563
to generate a transmit cell request every 563 CPM clocks:
Set FTIRRx_PHY0[TRM] to enable the transmit internal rate mode and clear
FTIRRx_PHY0[Initial Value] since there is no need to further divide the BRG. See
Section 29.13.4, ÒFCC Transmit Internal Rate Registers (FTIRRx).Ó
In external rate mode, however, the transmit cell request frequency is determined by the
PHYÕs maximum rate, not by internal FCC counters. If an OC-3 PHY is used with the ATM
controller in external rate mode, the requests must be generated every 362 CPM clocks
(assuming a 133-MHz CPM clock). If only 100 Mbps is used for real data, 36% of the
transmit cell requests consume CPM processing time sending idle cells.
29.16.2 APC ConÞguration
Maximizing the number of cells per slot (CPS) and minimizing the priority levels deÞned
in the APC data structure improves CPM performance:
¥ Cells per slot. CPS deÞnes the maximum number of ATM cells allowed to be sent
during a time slot. (See Section 29.3.3.1, ÒDetermining the Cells Per Slot (CPS) in
a Scheduling Table.Ó) The scheduling algorithm is more efÞcient sending multiple
cells per time slot using the linked-channel Þeld. Therefore, choose the maximum
number of cells per slot allowed by the application.
¥ Priority levels. The user can conÞgure the APC data structure to have from one to
eight priority levels. (See Section 29.3.6, ÒDetermining the Priority of an ATM
Channel.Ó) For each time slot, the scheduling algorithm scans all priority levels and
maintains pointers for each level. Therefore, enable only the minimum number of
priority levels required.
29.16.3 Buffer ConÞguration
Using statically allocated buffers of optimal sizes also improves CPM performance:
¥ Buffer size. Opening and closing buffer descriptors consumes CPM processing time.
Because smaller buffers require more opening and closing of BDs, the optimal
buffer size for maximum CPM performance is equal to the packet size (an AAL5
frame, for example).
¥ Free buffer pool. When the free buffer pool is used, the CPM dynamically allocates
buffers and links them to a channelÕs BD. In static buffer allocation, the core assigns
a Þxed data buffer to each BD. (See Section 29.10.5.2, ÒReceive Buffers
Operation.Ó) When allowed by the application, use static buffer allocation to
increase CPM performance.
133MHz 53 8
´ ( ) ´ ( )
100Mbps
----------------------------------------------------- 563 =