Motorola MPC8260 - Manual (Page 992)

Index-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
INDEX
programming model, 10-13
PSDVAL, 10-12, 10-57
register descriptions, 10-13
SDRAM machine (synchronous DRAM machine)
address multiplexing, 10-37
bank interleaving, 10-36
BSMA bit, 10-37
commands, JEDEC-standard, 10-35
common features, 10-6
configuration example, 10-48
implementation differences with UPMs and
GPCM, 10-7
JEDEC-standard commands, 10-35
MODE-SET command timing, 10-46
overview, 10-33
page mode support, 10-36
parameters
activate-to-read/write interval, 10-39
column address to first data out, 10-40
last data in to precharge, 10-41
last data out to precharge, 10-40
overview, 10-38
precharge-to-activate interval, 10-38
refresh recovery interval (RFRC), 10-41
pipeline accesses, 10-36
power-on initialization, 10-35
read/write transactions supported, 10-46
refresh, 10-47
SDAM bit, 10-37
supported configurations, 10-35
timing examples, 10-42
TEA generation, 10-9
UPMs (user-programmable machines)
access times, handling devices, 10-100
address control bits, 10-77
address multiplexing, 10-77
clock timing, 10-67
common features, 10-6
data sample control, 10-77
data valid, 10-77
differences between MPC8xx and MPC8260, 10-
80
DRAM configuration example, 10-79
EDO interface example, 10-92
exception requests, 10-66
hierarchical bus interface example, 10-100
implementation differences with SDRAM
machine and GPCM, 10-7
loop control, 10-76
memory access requests, 10-65
memory system interface example, 10-81
MPC8xx versus MPC8260, 10-80
overview, 10-62
programming the UPM, 10-66
RAM array, 10-69
RAM word, 10-70
refresh timer requests, 10-65
register settings, 10-80
requests, 10-64
signal negation, 10-78
signals, 10-62
software requests, 10-66
UPWAIT signal, 10-78
wait mechanism, 10-78
Memory management unit
overview, 2-8
Memory management unit overview, 2-26
Memory maps
cross-reference guide, 3-1
quick reference guide, 3-1
serial communications controllers (SCCs)
BISYNC mode, 22-4
HDLC mode, 21-4
UART mode, 20-4
serial management controllers (SMCs)
GCI mode, 26-30
transparent mode, 26-6
UART mode, 26-6
Microcode revision number, 13-10
Modes
60x bus mode
60x-compatible bus mode, 8-3
address latch enable (ALE), 10-11
data streaming mode, 8-27
extended transfer mode, 8-20
no-pipeline mode, 8-26
one-level pipeline mode, 8-26
single-MPC8260 bus mode, 8-2
ATM controller
APC modes, 29-8
external rate mode, 29-6
internal rate mode, 29-6
transmit rate modes, 29-6
BISYNC mode, 22-1
cascaded mode, 17-3
echo mode, 26-1
HDLC mode, 21-1
hunt mode, 20-10
IDMA emulation
edge-sensitive mode, 18-13
external request mode, 18-8
level-sensitive mode, 18-13
normal mode, 18-9
loopback mode, 26-1
NMSI mode, synchronization, 23-3
SCC AppleTalk mode, 25-1, 25-1
serial interface (SI)
echo mode, 14-7