Motorola MPC8260 - Manual (Page 356)

10-80 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
This means that the address bus should be partitioned as shown in Table 10-38.
From the device perspective, during RAS assertion, its address port should look like
Table 10-39:
Table 10-37 indicates that to multiplex A[8Ð19] over A[17Ð28], choose AMx = 001.
Table 10-40 shows the register conÞguration. Not shown are PURT and MPTPR, which
should be programmed according to the device refresh requirements.
10.6.6 Differences between MPC8xx UPM and MPC8260 UPM
Users familiar with the MPC8xx UPM should read this section Þrst.
Below is a list of the major differences between the MPC8xx devices and the MPC8260:
¥ First cycle timing transferred to the UPM arrayÑIn the MPC8xxÕs UPM, the Þrst
cycle value of some of the signals is determined from ORx[SAM,G5LA,G5LS].
This is eliminated in the MPC8260. All signals are controlled only by the pattern
written to the array.
Table 10-38. 60x Address Bus Partition
A[0Ð7] A[8Ð19] A[20Ð28] A[29Ð31]
msb of start address Row Column lsb
Table 10-39. DRAM Device Address Port during an ACTIVATE command
ТA[0Р16]У A[17Ð28] A[29Р31]
С Row (A[8Ð19]) n.c.
Table 10-40. Register Settings
Register Settings
BRx BA msb of base address
PS 00 = 64-bit port size
DECC 00
WP 0
MS 100 = UPMA
EMEMC 0
ATOM 00
DR 0
V 1
ORx AM 1111_1111_0000_0000_0 = 16 Mbyte
BI 0
EHTR 0
MxMR BSEL 0 = 60x bus
RFEN 1
OP 00
AM 001
DSA As needed
G0CLA N/A
GPL_A4DIS 0
RLFA As needed
WLFA As needed
TLFA As needed
MAD N/A