Motorola MPC8260 - Manual (Page 387)

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-5
Part III. The Hardware Interface
In ECC/parity mode the L2 cache can support memory regions with ECC/Parity under the
following restrictions:
¥ All non-write-protected (BRx[WP] = 0) memory banks marked caching-allowed
must use either ECC (BRx[DECC] = 0b11) or read-modify-write parity
(BRx[DECC] = 0b10). See Section 10.3.1, ÒBase Registers (BRx),Ó for more
information about the MPC8260 base register parameters.
¥ Only MPC8260-type masters are supported in systems that use ECC/parity L2 cache
mode. See Section 10.9, ÒExternal Master Support (60x-Compatible Mode),Ó for
more information about external master types.
Figure 11-3 shows a MPC8260 connected to an MPC2605 integrated L2 cache in ECC/
Parity mode.