Motorola MPC8260 - Manual (Page 267)

MOTOROLA Chapter 9. Clocks and Power Control 9-1
Chapter 9
Clocks and Power Control
90
90
The MPC8260Õs clocking architecture includes two PLLsÑthe main PLL and the core
PLL.
The clock block, which contains the main PLL, provides the following:
¥ Internal clocks for all blocks in the chip except core blocks
¥ The internal 60x bus clock in the chip
The core input clock has the 60x bus frequency, which the core PLL multiplies by a
conÞgurable factor and provides to all core blocks.
Seven bits, three that are dedicated (MODCK[1Ð3]) and four that are from the hardware
conÞguration word, (MODCK_H) map the MPC8260 clocks to one of 49 work options.
Each option determines the bus, core, and CPM frequencies. Assuming the four
conÞguration bits are zero, the three dedicated pins MODCK[1Ð3] select one of eight work
options, see Section 9.2, ÒClock ConÞguration.Ó
The CLOCKIN signal is the main timing reference for the MPC8260. The CLOCKIN
frequency is equal to the 60x and local bus frequencies. The main PLL can multiply the
frequency of the input clock to the Þnal CPM frequency.
9.1 Clock Unit
The MPC8260Õs clock module consists of the input clock interface (OSCM), the PLL, the
system frequency dividers, the clock generator/driver blocks, the conÞguration control unit,
and the clock control block. The clock module and the conÞguration control unit are
managed through the system clock mode register (SCMR), the conÞguration bits
MODCK[1Ð7], and reset block.
To improve noise immunity, the charge pump and the VCO of the main PLL have their own
set of power supply pins (VCCSYN and GNDSYN). All other circuits are powered by the
normal supply pins, VDD and VSS.