Motorola MPC8260 - Manual (Page 905)

MOTOROLA Chapter 31. FCC HDLC Controller 31-3
Part IV. Communications Processor Module
To rearrange the transmit queue before the CP has sent all buffers, issue the STOP TRANSMIT
command. This can be useful for sending expedited data before previously linked buffers
or for error situations. When receiving the
STOP TRANSMIT command, the HDLC controller
aborts the current frame transmission and starts transmitting idles or ßags. When the HDLC
controller is given the
RESTART TRANSMIT command, it resumes transmission. To insert a
high-priority frame without aborting the current frame, the GRACEFUL STOP TRANSMIT
command can be issued. A special interrupt (GRA) can be generated in the event register
when the current frame is complete.
31.3 HDLC Channel Frame Reception Processing
The HDLC receiver is designed to work with almost no core intervention and can perform
address recognition, CRC checking, and maximum frame length checking. The received
frame is available for any HDLC-based protocol. When the core enables a receiver, the
receiver waits for an opening ßag character. When it detects the Þrst byte of the frame, the
HDLC controller compares the frame address against the user-programmable addresses.
The user has four 16-bit address registers and an address mask available for address
matching. The HDLC controller compares the received address Þeld to the user-deÞned
values after masking with the address mask. The HDLC controller can also detect broadcast
(all ones) address frames if one address register is written with all ones.
If a match is detected, the HDLC controller checks the prefetched BD; if it is empty, it starts
transferring the incoming frame to the BDÕs associated buffer. When the buffer is full, the
HDLC controller clears BD[E] and generates an interrupt if BD[I] = 1. If the incoming
frame is larger than the buffer, the HDLC controller fetches the next BD in the table and, if
it is empty, continues transferring the frame to the associated buffer.
During this process, the HDLC controller checks for frames that are too long. When the
frame ends, the CRC Þeld is checked against the recalculated value and written to the
buffer. The data length written to the last BD in the HDLC frame is the length of the entire
frame. This enables HDLC protocols that lose frames to correctly recognize a frame-too-
long condition.
The HDLC controller then sets the last buffer in frame bit, writes the frame status bits into
the BD, and clears the E bit and fetched the next BD. The HDLC controller then generates
a maskable interrupt, indicating that a frame was received and is in memory. The HDLC
controller then waits for a new frame. Back-to-back frames can be received separated only
by a single shared ßag.
The user can conÞgure the HDLC controller not to interrupt the core until a speciÞed
number of frames have been received. This is conÞgured in the received frames threshold
(RFTHR) location of the parameter RAM. This function can be combined with a timer to
implement a time-out if fewer than the threshold number of frames are received.