Motorola MPC8260 - Manual (Page 982)

Index-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
INDEX
VBR traffic, 29-12
ATM TRANSMIT command, 29-90
ATM-to-ATM data forwarding, 29-37
ATM-to-TDM interworking, 29-34
buffer descriptors, 29-64
exceptions, 29-79
external rate mode, 29-6
FCCE, 29-87
FCCM, 29-87
features list, 29-2
FPSMR, 29-85
FTIRRx, 29-88
GFMR register, 29-85
global mode entry (GMODE), 29-41
internal rate mode, 29-6
interrupt queues, 29-79
maximum performance configuration, 29-92
OAM performance monitoring, 29-29, 29-60
OAM support, 29-27
operations and maintenance (OAM) support, 29-27
overview, 29-4
parameter RAM, 29-37
performance monitoring, 29-8
performance, maximum (configuration), 29-92
programming model, 29-85
receive connection table (RCT)
AALn protocol-specific RCTs, 29-46
ATM channel code, 29-42
overview, 29-41
raw cell queue, 29-19
RCT entry format, 29-44
registers, 29-85
RxBD, 29-69
RxBD extension, 29-73
SRTS generation using external logic, 29-91
transmit connection table (TCT)
AALn protocol-specific TCTs, 29-54
ATM channel code, 29-42
overview, 29-41
TCT entry format, 29-51
transmit connection table extension (TCTE)
ABR protocol-specific, 29-58
ATM channel code, 29-42
overview, 29-41
UBR+ protocol-specific, 29-57
VBR protocol-specific, 29-56
transmit rate modes, 29-6
TxBD, 29-74
TxBD extension, 29-78
UDC extended address mode, 29-33
UEAD_OFFSET determination, 29-40
UNI statistics table, 29-78
user-defined cells (UDC)
extended address mode, 29-33
overview, 29-32
RxBD extension (AAL5/AAL1), 29-73
TxBD extension (AAL5/AAL1), 29-78
user-defined RxBD extension
(AAL5/AAL1), 29-73
user-defined TxBD extension
(AAL5/AAL1), 29-78
UTOPIA interface, 29-82
VCI filtering, 29-40
VCI/VPI address lookup, 29-14
VC-level address compression tables
(VCLT), 29-18
VP-level address compression table
(VPLT), 29-17
B
Baud-rate generator (BRG)
BRGCLK, 34-2
memory map, 3-8
BCR (bus configuration register), 4-25
BDLE (SCC BISYNC DLE) register, 22-8
BISYNC mode
commands, 22-5
control character recognition, 22-6
error handling, 22-9
frame reception, 22-3
frame transmission, 22-2
frames, classes, 22-1
memory map, 22-4
overview, 22-1
parameter RAM, 22-3
programming example, 22-18
programming the controller, 22-17
receiving synchronization sequence, 22-9
RxBD, 22-12
sending synchronization sequence, 22-9
TxBD, 22-14
Block diagrams
cascaded mode, 17-4
communications processor (CP), 13-5
communications processor module (CPM), 13-3
CPM multiplexing logic (CMX), 15-2
DPLL receiver, 19-22
dual-bus architecture, 10-3
dual-port RAM, 13-15
Fast Ethernet, 30-3
FCC overview, 28-3
I
2 C controller, 34-1
IEEE 1149.1 test access port, 12-2
parallel I/O ports, 35-6
PLL block diagram, 9-5
SCC block diagram, 19-2
serial interface, 14-2
serial peripheral interface (SPI), 33-1