Motorola MPC8260 - Manual (Page 692)

24-24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
20. Initialize the TxBD and assume the Tx data frame is at 0x0000_2000 in main
memory and contains fourteen 8-bit characters (destination and source addresses
plus the type Þeld). Write 0xFC00 to TxBD[Status and Control], add PAD to the
frame and generate a CRC. Then write 0x000D to TxBD[Data Length] and
0x0000_2000 to TxBD[Buffer Pointer].
21. Write 0xFFFF to the SCCE register to clear any previous events.
22. Write 0x001A to the SCCM register to enable the TXE, RXF, and TXB interrupts.
23. Write 0x0040_0000 to the SIU interrupt mask register low (SIMR_L) so the SMC1
can generate a system interrupt. Initialize SIU interrupt pending register low
(SIPNR_L) by writing 0xFFFF_FFFF to it.
24. Write 0x0000_0000 to GSMR_H2 to enable normal operation of all modes.
25. Write 0x1088_000C to the GSMR_L2 register to conÞgure CTS (CLSN) and CD
(RENA) to automatically control transmission and reception (DIAG bits) and the
Ethernet mode. TCI is set to allow more setup time for the EEST to receive the
MPC8260 transmit data. TPL and TPP are set for Ethernet requirements. The DPLL
is not used with Ethernet. Note that the ENT and ENR are not enabled yet.
26. Write 0xD555 to the DSR.
27. Set the PSMR2 to 0x0A0A to conÞgure 32-bit CRC, promiscuous mode, and begin
searching for the start frame delimiter 22 bits after RENA2 (CD2).
28. Write 0x1088_003C to GSMR_L2 to enable the SCC2 transmitter and receiver. This
additional write ensures that ENT and ENR are enabled last.
After 14 bytes and the 46 bytes of automatic pad (plus the 4 bytes of CRC) are sent, the
TxBD is closed. Additionally, the receive buffer is closed after a frame is received. Any data
received after 1520 bytes or a single frame causes a busy (out-of-buffers) condition because
only one RxBD is prepared.