Motorola MPC8260 - Manual (Page 999)

MOTOROLA Index Index-19
INDEX
Serial peripheral interface (SPI)
block diagram, 33-1
clocking and pin functions, 33-2
commands, 33-12
configuring the SPI, 33-3
features list, 33-2
interrupt handling, 33-18
master mode, 33-3
maximum receive buffer length (MRBLR), 33-11
multi-master operation, 33-4
parameter RAM, 33-10
programming example
master, 33-16
slave, 33-17
programming model, 33-6
RxBD, 33-14
slave mode, 33-4
SPCOM, 33-9
SPIE, 33-9
SPIM, 33-9
SPMODE, 33-6
TxBD, 33-15
SI memory map, 3-13
SI RAM programming example, 14-13
SICR (SIU interrupt configuration register), 4-17
SIEXR (SIU external interrupt control register), 4-24
Signals
60x bus
TBST, 8-13
TCn, 8-13
TSIZn, 8-13
TTn, 8-10
byte-select signals, 10-75
chip-select signals, 10-74
clock signals, 9-6
general-purpose signals, 10-76, 10-76
IDMA emulation
DACKx, 18-13
DONEx, 18-14
DREQx, 18-13
memory controller
byte-select signals, 10-11
EAMUX, 10-41
PSDVAL, 10-12, 10-57
SDRAM interface signals, 10-33
UPM interface signals, 10-62
UPM signal negation, 10-78
UPWAIT, 10-78
overview, 6-2
SIPMR_H (SIU high interrupt mask register), 4-22
SIPMR_L (SIU low interrupt mask register), 4-22
SIPNR_H (SIU high interrupt pending register), 4-21
SIPNR_L (SIU low interrupt pending register), 4-21
SIPRR (SIU interrupt priority register), 4-18
SIU memory map, 3-1
SIUMCR (SIU module configuration register), 4-31
SIVEC (SIU interrupt vector register), 4-23
SMC memory map, 3-12
SMCE (SMC event) register
GCI mode, 26-34
transparent mode, 26-28
UART mode, 26-18
SMCM (SMC mask) register
GCI mode, 26-34
transparent mode, 26-28
UART mode, 26-18
SMCMRs (SMC mode registers), 26-3
SPCOM (SPI command) register, 33-9
SPI memory map, 3-12
SPIE (SPI event) register, 33-9
SPIM (SPI mask) register, 33-9
SPMODE (SPI mode) register, 33-6
SWR (software watchdog register), 4-7
SWSR (software service register), 4-36
SYPCR (system protection control register), 4-35
System integration timers memory map, 3-4
System interface unit (SIU)
60x bus monitor function, 4-2
BCR, 4-25
block diagram, 4-1
bus monitor, 4-3
clocks, 4-4
configuration functions, 4-2
configuration/protection logic block diagram, 4-3
encoding the interrupt vector, 4-14
FCC relative priority, 4-12
highest priority interrupt, 4-13
IMMR, 4-34
interrupt controller features list, 4-7
interrupt source priorities, 4-9
interrupt vector calculation, 4-14
interrupt vector encoding, 4-14
interrupt vector generation, 4-14
L_TESCR1, 4-38
L_TESCR2, 4-39
LCL_ACR, 4-29
LCL_ALRH, 4-30
LCL_ALRL, 4-30
local bus monitor function, 4-2
masking interrupt sources, 4-13
MCC relative priority, 4-12
periodic interrupt timer (PIT), 4-5
periodic interrupt timer (PIT) function, 4-2
pin multiplexing, 4-44
PISCR, 4-42
PITC, 4-43
PITR, 4-44
port C interrupts, 4-16
PPC_ACR, 4-28
PPC_ALRH, 4-28