Motorola MPC8260 - Manual (Page 790)

29-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Figure 29-1. APC Scheduling Table Mechanism
Each 2-byte time-slot entry points to one ATM channel. Additional channels scheduled to
transmit in the same slot are linked to each other using the APC linked-channel Þeld in the
TCT. The linked list is not limited; however, if the number of channels for the current slot
exceeds the cells per slot parameter (CPS), the extra channels are sent in subsequent time
slots. (The rescheduling of extra channels is based on the original slot to maintain each
channelÕs pace.)
Note that a channel can appear only once in the scheduling table at a given time, because
each channel has only one APC linked-channel Þeld.
29.3.3 Determining the Scheduling Table Size
The following sections describe how to determine the number of cells sent per time slot and
the total number of slots needed in a scheduling table.
29.3.3.1 Determining the Cells Per Slot (CPS) in a Scheduling Table
The number of cells sent per time slot is determined by the channel with the maximum bit
rate; see equation A. The maximum bit rate is achieved when a channel is rescheduled to
the next slot. For example, if the line rate is 155.52 Mbps and there are eight cells per slot,
equation A yields a maximum VC rate of 19.44 Mbps.
Note that a channel can appear only once per time slot; thus, 19.44 Mbps = 155.52Mbps/8.
The cells per slot parameter (CPS) affects the cell delay variation (CDV). Because the APC
unit does not put cells in a deÞnite order within each time slot (LIFOÑlast-in/Þrst-out
implementation), as CPS increases, the CDV increases. However as CPS decreases, the size
of the scheduling table in the dual-port RAM increases and more CPM bandwidth is
required.
1
5
9
4
6
7 8 2
3
Cells per Slot
Number of Slots
Current Slot Cell Rescheduling
Max bit rate = (A)
line rate
cells per slot