Motorola MPC8260 - Manual (Page 95)

MOTOROLA Chapter 2. PowerPC Processor Core 2-7
Part I. Overview
2.2.4.2 Load/Store Unit (LSU)
The LSU executes all load and store instructions and provides the data transfer interface
between the GPRs, FPRs, and the cache/memory subsystem. The LSU calculates effective
addresses, performs data alignment, and provides sequencing for load/store string and
multiple instructions.
Load and store instructions are issued and translated in program order; however, the actual
memory accesses can occur out of order. Synchronizing instructions are provided to
enforce strict ordering where needed.
Cacheable loads, when free of data dependencies, execute in an out-of-order manner with
a maximum throughput of one per cycle and a two-cycle total latency. Data returned from
the cache is held in a rename register until the completion logic commits the value to a GPR
or FPR. Store operations do not occur until a predicted branch is resolved. They remain in
the store queue until the completion logic signals that the store operation is deÞnitely to be
completed to memory.
The processor core executes store instructions with a maximum throughput of one per cycle
and a three-cycle total latency. The time required to perform the actual load or store
operation varies depending on whether the operation involves the cache, system memory,
or an I/O device.
2.2.4.3 System Register Unit (SRU)
The SRU executes various system-level instructions, including condition register logical
operations and move to/from special-purpose register instructions, and also executes
integer add/compare instructions. Because SRU instructions affect modes of processor
operation, most SRU instructions are completion-serialized. That is, the instruction is held
for execution in the SRU until all prior instructions issued have completed. Results from
completion-serialized instructions executed by the SRU are not available or forwarded for
subsequent instructions until the instruction completes.
2.2.5 Completion Unit
The completion unit tracks instructions from dispatch through execution, and then retires,
or completes them in program order. Completing an instruction commits the processor core
to any architectural register changes caused by that instruction. In-order completion ensures
the correct architectural state when the processor core must recover from a mispredicted
branch or any exception.
Instruction state and other information required for completion is kept in a Þrst-in-Þrst-out
(FIFO) queue of Þve completion buffers. A single completion buffer is allocated for each
instruction once it enters the dispatch unit. An available completion buffer is a required
resource for instruction dispatch; if no completion buffers are available, instruction
dispatch stalls. A maximum of two instructions per cycle are completed in order from the
queue.