Motorola MPC8260 - Manual (Page 422)

12-30 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
The parallel output of the instruction register is set to all ones in the test-logic-reset
controller state. Notice that this preset state is equivalent to the BYPASS instruction.
During the capture-IR controller state, the parallel inputs to the instruction shift register are
loaded with the CLAMP command code.
12.5 MPC8260 Restrictions
The control afforded by the output enable signals using the boundary-scan register and the
EXTEST instruction requires a compatible circuit-board test environment to avoid
device-destructive conÞgurations. The user must avoid situations in which the MPC8260Õs
output drivers are enabled into actively driven networks.
12.6 Nonscan Chain Operation
In nonscan chain operation, the TCK input does not include an internal pull-up resistor and
should be tied high or low to preclude mid-level inputs.
To ensure that the scan chain test logic is kept transparent to the system logic, the TAP
controller is forced into the test-logic-reset state. This is done inside the chip by connecting
TRST to PORESET
TMS should remain connected to V
cc
or should not change state, so that the TAP controller
will not leave the test-logic-reset state.