Motorola MPC8260 - Manual (Page 986)

Index-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
INDEX
master write (slave read), 34-4
multi-master considerations, 34-5
parameter RAM, 34-9
programming model, 34-6
registers, 34-6
RxBD, 34-13
slave read (master write), 34-4
slave write (master read), 34-4
transfers, 34-3
TxBD, 34-14
IDMA emulation
auto buffer, 18-15
buffer chaining, 18-15
buffers, 18-23
bus exceptions, 18-27
commands, 18-26
controlling 60x bus bandwidth, 18-12
DACKx, 18-13
DCM, 18-18
DONEx, 18-14
DREQx, 18-13
DTS/STS programming, 18-20
dual-address transfers, 18-10
edge-sensitive mode, 18-13
exceptions, bus, 18-27
external request mode, 18-8
features list, 18-5
IDMR, 18-22
IDSR, 18-22
level-sensitive mode, 18-13
normal mode, 18-9
operand transfers, recognizing, 18-27
operation, 18-14
overview, 18-5
parallel I/O register programming, 18-28
parameter RAM, 18-16
priorities, 18-12
programming examples, 18-29
programming the parallel I/O registers, 18-28
signals, 18-12
single address transfers (fly-by), 18-11
transfers, 18-6
interrupt controller
memory map, 3-4
multi-channel controllers (MCCs)
CHAMR
HDLC mode, 27-10
transparent mode, 27-13
channel extra parameters, 27-5
commands, 27-16
data structure organization, 27-2
exceptions, 27-17
features list, 27-1
global parameters, 27-3
HDLC parameters (channel-specific), 27-8
initialization, 27-24
INTMSK, 27-9
latency, 27-26
MCCE, 27-18
MCCFx, 27-15
MCCM, 27-18
parameters for transparent operation, 27-12
performance, 27-26
receive commands, 27-17
RSTATE, 27-11
RxBD, 27-21
super channel table, 27-5
TSTATE, 27-9
TxBD, 27-23
overview, CPM, 13-1
parallel I/O ports
block diagram, 35-6
features, 35-1
overview, 35-1
PDATx, 35-2
PDIRx, 35-3
pin assignments (port AÐport D), 35-8Ð35-19
PODRx, 35-2
port C interrupts, 35-19
port pin functions, 35-6
PPAR, 35-4
programming options, 35-8
PSORx, 35-4
registers, 35-2
resetting registers and parameters for
all channels, 13-11
RISC timer tables
CP loading tracking, 13-24
features list, 13-19
initializing RISC timer tables, 13-22
interrupt handling, 13-23
overview, 13-18
parameter RAM, 13-19
pulse width modulation (PWM) channels, 13-19
RAM usage, 13-19
RTER, 13-21
RTMR, 13-21
scan algorithm, 13-23
SET TIMER command, 13-22
table entries, 13-21
timer counts, comparing, 13-24
TM_CMD, 13-20
tracking CP loading, 13-24
SDMA channels
bus arbitration, 18-2
bus transfers, 18-2
LDTEA, 18-4
LDTEM, 18-4