Motorola MPC8260 - Manual (Page 855)

29-75 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 29-38 describes AAL5 TxBD Þelds.
Table 29-38. AAL5 TxBD Field Descriptions
Offset Bits Name Description
0x00 0 R Ready
0 The buffer associated with this BD is not ready for transmission. The user is free to
manipulate this BD or its associated buffer. The CP clears R after the buffer is sent or
after an error condition is encountered.
1 The user-prepared buffer has not been sent or is currently being sent. No Þelds of this
BD may be written by the user once R is set.
1 Ñ Reserved, should be cleared.
2 W Wrap (Þnal BD in table)
0 Not the last BD in the TxBD table.
1 Last BD in the TxBD table. After this buffer is used, the CP sends outgoing data from
the Þrst BD in the table (the BD pointed to by the channelÕs TCT[TBD_BASE]). The
number of TxBDs in this table is determined only by the W bit. The current table cannot
exceed 64 Kbytes.
3 I Interrupt
0 No interrupt is generated after this buffer has been serviced.
1 A Tx Buffer event is sent to the interrupt queue after this buffer is serviced.
FCCE[GINTx] is set when the INT_CNT counter reaches the global interrupt threshold.
4 L Last in frame. Set by the user to indicate the last buffer in a frame.
0 Buffer is not last in a frame.
1 Buffer is last in a frame.
5 Ñ Reserved, should be cleared.
6 CM Continuous mode
0 Normal operation.
1 The CP does not clear R after this BD is closed, allowing the associated buffer to be
retransmitted automatically when the CP next accesses this BD. However, the R bit is
cleared if an error occurs during transmission, regardless of CM.
7-9 Ñ Reserved, should be cleared.
10 CLP The ATM cell header CLP bit of the cells associated with the current frame are ORed
with this Þeld. This Þeld is valid only in the Þrst BD of the frame.
11 CNG The ATM cell header CNG bit of the cells associated with the current frame are ORed
with this Þeld. This Þeld is valid only in the Þrst BD of the frame.
12Р15 С Reserved, should be cleared.
0x02 Ñ DL The number of octets the ATM controller should transmit from this BDÕs buffer. It is not
modiÞed by the CP. The value of DL should be greater than zero.
0x04 Ñ TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer, which may or may
not be 8-byte-aligned. The buffer may reside in either internal or external memory. This
value is not modiÞed by the CP.