Motorola MPC8260 - Manual (Page 329)

MOTOROLA Chapter 10. Memory Controller 10-53
Part III. The Hardware Interface
10.5.1.1 Chip-Select Assertion Timing
From 0 to 30 wait states can be programmed for PSDVAL generation. Byte-write enable
signals (WE) are available for each byte written to memory. Also, the output enable signal
(OE) is provided to eliminate external glue logic. The memory banks selected to work with
the GPCM have unique features. On system reset, a global (boot) chip-select is available
that provides a boot ROM chip-select prior to the system being fully conÞgured. The banks
selected to work with the GPCM support an option to output the CS line at different timings
with respect to the external address bus. CS can be output in any of three conÞgurations:
¥ Simultaneous with the external address
¥ One quarter of a clock cycle later
¥ One half of a clock cycle later
Figure 10-41 shows a basic connection between the MPC8260 and an external peripheral
device. Here, CS (the strobe output for the memory access) is connected directly to CE of
the memory device and BCTL0 is connected to the respective R/W in the peripheral device.
Figure 10-41. GPCM Peripheral Device Interface
Figure 10-42 shows CS as deÞned by the setup time required between the address lines and
CE. The user can conÞgure ORx[ACS] to specify CS to meet this requirement.
Figure 10-42. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0)
Address
CE
R/W
Data
Peripheral
Data
BCTL0
CS
Address
MPC8260
Clock
Address
PSDVAL
CS
OE
Data
ACS = 11
ACS = 10