Motorola MPC8260 - Manual (Page 186)

5-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part II. ConÞguration and Reset
5.1.1 Reset Actions
The reset block has a reset control logic that determines the cause of reset, synchronizes it
if necessary, and resets the appropriate logic modules. The memory controller, system
protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset.
Soft reset initializes the internal logic while maintaining the system conÞguration.
Table 5-2 identiÞes reset actions for each reset source.
5.1.2 Power-On Reset Flow
Assertion of the PORESET external pin initiates the power-on reset ßow. PORESET should
be asserted externally for at least 16 input clock cycles after external power to the chip
reaches at least 2/3 Vcc. The value driven on RSTCONF while PORESET changes from
assertion to negation determines the chip conÞguration. If RSTCONF is negated (driven
high) while PORESET changes, the chip acts as a conÞguration slave. If RSTCONF is
asserted while PORESET changes, the chip acts as a conÞguration master. Section 5.4,
ÒReset ConÞguration,Ó explains the conÞguration sequence and the terms ÔconÞguration
masterÕ and ÔconÞguration slave.Õ
Directly after the negation of PORESET and choice of the reset operation mode as
conÞguration master or conÞguration slave, the MPC8260 starts the conÞguration process.
The MPC8260 asserts HRESET and SRESET throughout the power-on reset process,
including conÞguration. ConÞguration takes 1,024 CLOCKIN cycles, after which
MODCK[1Ð3] are sampled to determine the chips working mode. Next the MPC8260 halts
until the main PLL locks. As described in Section 9.2, ÒClock ConÞguration,Ó the main
PLL locks according to MODCK[1Ð3], which are sampled, and to MODCK_HI
(MODCK[4Ð7]) taken from the reset conÞguration word. The main PLL lock can take up
to 200 µs depending on the speciÞc chip. During this time HRESET and SRESET are
asserted. When the main PLL is locked, the clock block starts distributing clock signals in
the chip. HRESET remains asserted for another 512 clocks and is then released. The
SRESET is released three clocks later.
Table 5-2. Reset Actions for Each Reset Source
Reset Source
Reset Logic
and PLL
States Reset
System
ConÞguration
Sampled
Clock
Module
Reset
HRESET
Driven
Other
Internal
Logic Reset
SRESET
Driven
Core
Reset
Power-on reset Yes Yes Yes Yes Yes Yes Yes
External hard reset
Software watchdog
Bus monitor
Checkstop No Yes Yes Yes Yes Yes Yes
JTAG reset
External soft reset No No No No Yes Yes Yes