Motorola MPC8260 - Manual (Page 878)

30-4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
¥ Multibuffer data structure
¥ Supports 48-bit addresses in three modes
Ñ Physical. One 48-bit address recognized or 64-bin hash table for physical
addresses
Ñ Logical. 64-bin group address hash table plus broadcast address checking
Ñ Promiscuous. Receives all frames regardless of address (a CAM can be used for
address Þltering)
¥ External CAM support on system bus interfaces
¥ Special RMON counters for monitoring network statistics
¥ Up to eight parallel I/O pins can be sampled and appended to any frame
¥ Transmitter network management and diagnostics
Ñ Lost carrier sense
Ñ Underrun
Ñ Number of collisions exceeded the maximum allowed
Ñ Number of retries per frame
Ñ Deferred frame indication
Ñ Late collision
¥ Receiver network management and diagnostics
Ñ CRC error indication
Ñ Nonoctet alignment error
Ñ Frame too short
Ñ Frame too long
Ñ Overrun
Ñ Busy (out of buffers)
¥ Error counters
Ñ Discarded frames (out of buffers or overrun occurred)
Ñ CRC errors
Ñ Alignment errors
¥ Internal and external loopback mode
¥ Supports Fast Ethernet in duplex mode
¥ Supports pause ßow control frames
¥ Support of out-of-sequence transmit queue (for ßow-control frames)
¥ External buffer descriptors (BDs)
30.3 Connecting the MPC8260 to Fast Ethernet
Figure 30-3 shows the basic components of the media-independent interface (MII) and the
signals required to make the Fast Ethernet connection between the MPC8260 and a PHY.