MOTOROLA
Chapter 11. Secondary (L2) Cache Support
11-9
Part III. The Hardware Interface
Figure 11-4. Read Access with L2 Cache
CLK
BR
BG
Addr
TS
ABB
A0 & TBST& CI
Memc controls
AACK
DBG
DBB
DATA
TA
D00
active
A1 & TBST
D01
D02
D03
L2 HIT
L2D = 0
0
L2
disabled
MPC8260
0