Motorola MPC8260 - Manual (Page 93)

MOTOROLA Chapter 2. PowerPC Processor Core 2-5
Part I. Overview
¥ Integrated power management
Ñ Three power-saving modes: doze, nap, and sleep
Ñ Automatic dynamic power reduction when internal functional units are idle
¥ Deterministic behavior and debug features
Ñ On-chip cache locking options for the instruction and data caches (1Ð3 ways or
the entire cache contents can be locked)
Ñ In-system testability and debugging features through JTAG and boundary-scan
capability
Figure 2-1 shows how the execution unitsÑIU, BPU, LSU, and SRUÑoperate
independently and in parallel. Note that this is a conceptual diagram and does not attempt
to show how these features are physically implemented on the chip.
The processor core provides address translation and protection facilities, including an
ITLB, DTLB, and instruction and data BAT arrays. Instruction fetching and issuing is
handled in the instruction unit. The MMUs translate addresses for cache or external
memory accesses.
2.2.1 Instruction Unit
As shown in Figure 2-1, the instruction unit, which contains a fetch unit, instruction queue,
dispatch unit, and the BPU, provides centralized control of instruction ßow to the execution
units. The instruction unit determines the address of the next instruction to be fetched based
on information from the sequential fetcher and from the BPU.
The instruction unit fetches the instructions from the instruction cache into the instruction
queue. The BPU extracts branch instructions from the fetcher and uses static branch
prediction on unresolved conditional branches to allow the instruction unit to fetch
instructions from a predicted target instruction stream while a conditional branch is
evaluated. The BPU folds out branch instructions for unconditional branches or conditional
branches unaffected by instructions in progress in the execution pipeline.
Instructions issued beyond a predicted branch do not complete execution until the branch
is resolved, preserving the programming model of sequential execution. If any of these
instructions are to be executed in the BPU, they are decoded but not issued. Instructions to
be executed by the IU, LSU, and SRU are issued and allowed to complete up to the register
write-back stage. Write-back is allowed when a correctly predicted branch is resolved, and
instruction execution continues without interruption on the predicted path. If branch
prediction is incorrect, the instruction unit ßushes all predicted path instructions, and
instructions are issued from the correct path.
2.2.2 Instruction Queue and Dispatch Unit
The instruction queue (IQ), shown in Figure 2-1, holds as many as six instructions and
loads up to two instructions from the instruction unit during a single cycle. The instruction
fetch unit continuously loads as many instructions as space in the IQ allows. Instructions