Motorola MPC8260 - Manual (Page 987)

MOTOROLA Index Index-7
INDEX
overview, 18-1
PDTEA, 18-4
PDTEM, 18-4
programming model, 18-3
registers, 18-3
SDMR, 18-4
SDSR, 18-3
serial configuration, 13-3
serial peripheral interface (SPI)
block diagram, 33-1
clocking and pin functions, 33-2
commands, 33-12
configuring the SPI, 33-3
features list, 33-2
interrupt handling, 33-18
master mode, 33-3
maximum receive buffer length (MRBLR), 33-11
multi-master operation, 33-4
parameter RAM, 33-10
programming example
master, 33-16
slave, 33-17
programming model, 33-6
RxBD, 33-14
slave mode, 33-4
SPCOM, 33-9
SPIE, 33-9
SPIM, 33-9
SPMODE, 33-6
TxBD, 33-15
system interface unit (SIU)
60x bus monitor function, 4-2
add flexibility to CPM interrupt priorities, 4-12
BCR, 4-25
block diagram, 4-1
bus monitor, 4-3
clocks, 4-4
configuration functions, 4-2
configuration/protection logic block diagram, 4-3
encoding the interrupt vector, 4-14
FCC relative priority, 4-12
flexibility of interrupt priorities, 4-12
highest priority interrupt, 4-13
IMMR, 4-34
interrupt controller features list, 4-7
interrupt priorities, add flexibility, 4-12
interrupt source priorities, 4-9
interrupt vector calculation, 4-14
interrupt vector encoding, 4-14
interrupt vector generation, 4-14
L_TESCR1, 4-38
L_TESCR2, 4-39
LCL_ACR, 4-29
LCL_ALRH, 4-30
LCL_ALRL, 4-30
local bus monitor function, 4-2
masking interrupt sources, 4-13
MCC relative priority, 4-12
periodic interrupt timer (PIT), 4-5
periodic interrupt timer (PIT) function, 4-2
pin multiplexing, 4-44
PISCR, 4-42
PITC, 4-43
PITR, 4-44
port C interrupts, 4-16
PPC_ACR, 4-28
PPC_ALRH, 4-28
PPC_ALRL, 4-29
programming model, 4-17
registers, 4-17
SCC relative priority, 4-12
SCPRR_H, 4-19
SCPRR_L, 4-20
SICR, 4-17
SIEXR, 4-24
signal multiplexing, 4-44
SIMR_H, 4-22
SIMR_L, 4-22
SIPNR_H, 4-21
SIPNR_L, 4-21
SIPRR, 4-18
SIUMCR, 4-31
SIVEC, 4-23
software watchdog timer, 4-6
SWR, 4-7
SWSR, 4-36
SYPCR, 4-35
system protection, 4-2
TESCR1, 4-36
TESCR2, 4-37
time counter (TMCNT)
function, 4-2
overview, 4-4
timers, 4-4
TMCNT, 4-41
TMCNTAL, 4-41
TMCNTSC, 4-40
timers
memory map, 3-5
Conventions
notational conventions, lx, II-ii, III-ii, IV-iv
terminology, lxiv
CPCR (CP command register), 13-11
CPM multiplexing logic (CMX)
overview, 15-1
see also Serial interface (SI)
CPM multiplexing, see CPM multiplexing
logic (CMX)
CPM MUX memory map, 3-12
CPM MUX, see CPM multiplexing logic (CMX)