Index – Motorola MPC8260 User Manual

Page 985

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MOTOROLA

Index Index-5

INDEX

command register example, 13-15
CPCR, 13-11
opcodes, 13-13
overview, 13-11

communications processor (CP)

block diagram, 13-5
execution from RAM, 13-7
features list, 13-4
interfacing with the core, 13-6
microcode execution from RAM, 13-7
microcode revision number, 13-10
peripheral interface, 13-6
PowerPC core interface, 13-6
RCCR, 13-7
REV_NUM, 13-10
RTSCR, 13-9
RTSR, 13-10

CPM multiplexing logic (CMX)

block diagram, 15-2
overview, 15-1

dual-port RAM

accessing dual-port RAM, 13-15
block diagram, 13-15
buffer descriptors, 13-17
memory map, 13-16
overview, 13-15
parameter RAM, 13-17

fast communications controllers (FCCs)

Fast Ethernet mode

address recognition, 30-15
block diagram, 30-3
CAM interface, 30-8
collision handling, 30-18
connecting to the MPC8260, 30-4
error handling, 30-19
FCCE, 30-21
FCCM, 30-21
features list, 30-3
FPSMR, 30-20
frame reception, 30-7
frame transmission, 30-5
hash table algorithm, 30-17
hash table effectiveness, 30-17
interpacket gap time, 30-18
interrupt events, 30-23
loopback mode, 30-18
parameter RAM, 30-9
programming model, 30-12
registers, 30-19
RMON support, 30-14
RxBD, 30-23
TxBD, 30-26

HDLC mode

bit stuffing, 31-1
error control, 31-1

error handling, 31-6
FCCE, 31-14
FCCM, 31-14
FCCS, 31-16
features list, 31-2
FPSMR, 31-7
frame reception, 31-3
frame transmission, 31-2
overview, 31-1
parameter RAM, 31-4
programming model, 31-5
receive commands, 31-6
reception errors, 31-7
RxBD, 31-9
transmission errors, 31-6
transmit commands, 31-5
TxBD, 31-12

overview

block diagram, 28-3
disabling FCCs, 28-19
FCCEx, 28-14
FCCMx, 28-14
FCCSx, 28-14
FCRx, 28-13
FDSRx, 28-7
FPSMRx, 28-7
FTODRx, 28-7
GFMRx, 28-3
initialization, 28-14
interrupt handling, 28-15
interrupts, 28-13
overview, 28-2
parameter RAM, 28-10
RxBD, 28-8
saving power, 28-21
switching protocols, 28-21
timing control, 28-15
TxBD, 28-8

transparent mode

achieving synchronization, 32-2
external synchronization signals, 32-3
features list, 32-2
in-line synchronization pattern, 32-3
receive operation, 32-2
synchronization example, 32-4
transmit operation, 32-2

features list, 13-1
I

2

C controller

block diagram, 34-1
BRGCLK, 34-2
clocking and pin functions, 34-2
commands, 34-11
features list, 34-2
loopback testing, 34-4
master read (slave write), 34-4

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