Motorola MPC8260 - Manual (Page 748)

27-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
end of the table). When an MCC channel generates an interrupt request, the CP writes a new
entry to the table (with V = 1) and increments T/RINTPTR (if W = 1 for the current entry,
T/RINTPTR is loaded with T/RINTBASE).
An interrupt is issued to the core whenever an entry is added to an interrupt circular table,
except for the RXF events (received complete HDLC frame), in which case an interrupt is
issued after a total of GRFTHR entries were added to one or more of the receive interrupt
circular tables. See Table 27-1 for the description of the GRFTHR.
In addition to the channelÕs number, this entry contains a description of the exception (see
Section 27.10.1.1, ÒInterrupt Table EntryÓ).
After an MCC interrupt, the user reads MCCE. MCCE[GINT] can be used to indicate that
at least one new entry was added to one of the tables. After clearing GINT, the user starts
processing the table(s) which contain pending events, as indicated by the bits
MCCE[RINTx] and MCCE[TINT]. The user then clears this entryÕs valid bit (V) (see
Section 27.10.1.1, ÒInterrupt Table EntryÓ). The user follows this procedure until it reaches
an entry with V = 0.
27.10.1 MCC Event Register (MCCE)/Mask Register (MCCM)
The MCC event register (MCCE) is used to report events and generate interrupt requests.
For each of its ßags, a programmable mask/enable bit in MCCM determines whether an
interrupt request is generated. The MCC mask register (MCCM) is used to enable/disable
interrupt requests. For each ßag in the MCCE there is a programmable mask/enable bit in
MCCM which determines whether an interrupt request is generated. Setting an MCCM bit
enables and clearing an MCCM bit disables the corresponding interrupt.
MCCE bits are cleared by writing ones to them; writing zeros has no effect.
Figure 27-13 shows MCCE and MCCM bits,
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field QOV0 RINT0 QOV1 RINT1 QOV2 RINT2 QOV3 RINT3 Ñ TQOV TINT GUN GOV
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11B30 (MCCE1), 0x11B50 (MCCE2)/0x11B34 (MCCM1), 0x11B54 (MCCM2)
Figure 27-13. MCC Event Register (MCCE)/Mask Register (MCCM)