Motorola MPC8260 - Manual (Page 337)

MOTOROLA Chapter 10. Memory Controller 10-61
Part III. The Hardware Interface
Figure 10-54. External Termination of GPCM Access
10.5.3 Boot Chip-Select Operation
Boot chip-select operation allows address decoding for a boot ROM before system
initialization. The CS0 signal is the boot chip-select output; its operation differs from the
other external chip-select outputs on system reset. When the MPC8260 internal core begins
accessing memory at system reset, CS0 is asserted for every address in the boot address
range, unless an internal register is accessed. The address range is conÞgured during reset.
The boot chip-select also provides a programmable port size during system reset by using
the conÞguration mechanism described in Section 5.4, ÒReset ConÞguration.Ó The boot
chip-select does not provide write protection. CS0 operates this way until the Þrst write to
OR0 and it can be used as any other chip-select register once the preferred address range is
loaded into BR0. After the Þrst write to OR0, the boot chip-select can be restarted only on
hardware reset. Table 10-32 describes the initial values of the boot bank in the memory
controller.
Clock
Address
R/W
CS
OE
D
GTA
PSDVAL