Spi transfer format with spmode[cp] = 0 -7, Spi transfer format with spmode[cp] = 1 -7, See figure 33-5 and figure 33-6 – Motorola MPC8260 User Manual

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Chapter 33. Serial Peripheral Interface (SPI)

33-7

Part IV. Communications Processor Module

Figure 33-5. SPI Transfer Format with SPMODE[CP] = 0

Figure 33-6 shows the SPI transfer format in which SPICLK starts toggling at the
beginning of the transfer (SPMODE[CP] = 1).

Figure 33-6. SPI Transfer Format with SPMODE[CP] = 1

Enable SPI. Do not change other SPMODE bits when EN is set.
0 The SPI is disabled. The SPI is in a reset state and consumes minimal power. The SPI BRG is not

functioning and the input clock is disabled.

1 The SPI is enabled. ConÞgure SPIMOSI, SPIMISO, SPICLK, and SPISEL to connect to the SPI as

described in Section 35.2, ÒPort Registers. Т

8Р11

LEN

Character length in bits per character. Must be between 0011 (4 bits) and 1111 (16 bits). A value less
than 4 causes erratic behavior. If the value is not greater than a byte, every byte in memory holds LEN
valid bits. If the value is greater than a byte, every half-word holds LEN valid bits. See
Section 33.4.1.1, ÒSPI Examples with Different SPMODE[LEN] Values.У

12Р15 PM

Prescale modulus select. SpeciÞes the divide ratio of the prescale divider in the SPI clock generator.
BRGCLK is divided by 4 * ([PM0ÐPM3] + 1), a range from 4 to 64. The clock has a 50% duty cycle.

Table 33-1. SPMODE Field Descriptions (Continued)

Bits

Name

Description

SPICLK

SPIMOSI

SPISEL

(From Master)

SPIMISO

(From Slave)

(CI = 0)

(CI = 1)

NOTE: Q = Undefined Signal.

msb

lsb

msb

lsb