Motorola MPC8260 - Manual (Page 423)

MOTOROLA Part IV. Communications Processor Module Part IV-i
Part IV
Communications Processor Module
Intended Audience
Part IV is intended for system designers who need to implement various communications
protocols on the MPC8260. It assumes a basic understanding of the PowerPC exception
model, the MPC8260 interrupt structure, as well as a working knowledge of the
communications protocols to be used. A complete discussion of these protocols is beyond
the scope of this book.
Contents
Part IV describes behavior of the MPC8260 communications processor module (CPM) and
the RISC communications processor (CP) that it contains (note that this is separate from
the embedded PowerPC processor).
It contains the following chapters:
¥ Chapter 13, ÒCommunications Processor Module Overview,Ó provides a brief
overview of the MPC8260 CPM.
¥ Chapter 14, ÒSerial Interface with Time-Slot Assigner,Ó describes the SIU, which
controls system start-up, initialization and operation, protection, as well as the
external system bus.
¥ Chapter 15, ÒCPM Multiplexing,Ó describes the CPM multiplexing logic (CMX)
which connects the physical layerÑUTOPIA, MII, modem lines,
¥ Chapter 16, ÒBaud-Rate Generators (BRGs),Ó describes the eight independent,
identical baud-rate generators (BRGs) that can be used with the FCCs, SCCs, and
SMCs.
¥ Chapter 17, ÒTimers,Ó describes the MPC8260 timer implementation, which can be
conÞgured as four identical 16-bit or two 32-bit general-purpose timers.
¥ Chapter 18, ÒSDMA Channels and IDMA Emulation,Ó describes the two physical
serial DMA (SDMA) channels on the MPC8260.