Motorola MPC8260 - Manual (Page 639)

MOTOROLA Chapter 22. SCC BISYNC Mode 22-7
Part IV. Communications Processor Module
Table 22-4 describes control character table and RCCM Þelds.
22.7 BISYNC SYNC Register (BSYNC)
The BSYNC register deÞnes BISYNC stripping and SYNC character insertion. When an
underrun occurs, the BISYNC controller inserts SYNC characters until the next buffer is
available for transmission. If the receiver is not in hunt mode when a SYNC character is
received, it discards this character if the valid bit (BSYNC[V]) is set.When using 7-bit
characters with parity, the parity bit should be included in the SYNC register value.
Table 22-4. Control Character Table and RCCM Field Descriptions
Offset Bit Name Description
0x42Ð
0x50 0 E End of table.
0 This entry is valid. The lower eight bits are checked against the incoming character.
In tables with eight control characters, E should be zero in all eight positions.
1 The entry is not valid. No other valid entries exist beyond this entry.
1 B BCS expected. A maskable interrupt is generated after the buffer is closed.
0 The character is written into the receive buffer and the buffer is closed.
1 The character is written into the receive buffer. The receiver waits for one LRC or
two CRC bytes of BCS and then closes the buffer. This should be used for ETB,
ETX, and ITB.
2 H Hunt mode. Enables hunt mode when the current buffer is closed.
0 The BISYNC controller maintains character synchronization after closing this buffer.
1 The BISYNC controller enters hunt mode after closing the buffer. When the B bit is
set, the controller enters hunt mode after receiving the BCS.
3Р7 С Reserved
8Ð15 CHARACTERn Control character 1Ð8. When using 7-bit characters with parity, include the parity bit in
the character value.
0x52 0Р2 С All ones.
3Р7 С Reserved
8Ð15 RCCM Received control character mask. Masks comparison of CHARACTERn. Each bit of
RCCM masks the corresponding bit of CHARACTERn.
0 Mask this bit in the comparison of the incoming character and CHARACTERn.
1 The address comparison on this bit proceeds normally and no masking occurs. If
RCCM is not set, erratic operation can occur during control character recognition.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field V DIS 0 0 0 0 0 0 SYNC
Reset UndeÞned
R/W R/W
Address SCC Base + 0x3E
Figure 22-3. BISYNC SYNC (BSYNC)