Motorola MPC8260 - Manual (Page 476)

14-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Figure 14-16 shows the effects of changing FE when CE = 1 with no frame sync delay.
Figure 14-16. Falling Edge (FE) Effect When CE = 1 and xFSD = 00
L1TXD
L1ST
L1SYNC
L1CLK
(Bit-0)
(On Bit-0)
xFSD=00
(FE=0)
CE=1
The L1ST is Driven from Sync.
Data is Driven from Clock Low.
L1TXD
L1ST
L1SYNC
(Bit-0)
(On Bit-0)
(FE=0)
L1ST is Driven from Clock High.
L1TXD
L1ST
L1SYNC
(Bit-0)
(On Bit-0)
(FE=1)
Both Data Bit-0 and L1ST are
Driven from Sync.
Rx Sampled Here
Rx Sampled Here
L1TXD
L1ST
L1SYNC
(Bit-0)
(On Bit-0)
(FE=1)
L1ST and Data Bit-0 is Driven
from Clock Low.