Motorola MPC8260 - Manual (Page 351)

MOTOROLA Chapter 10. Memory Controller 10-75
Part III. The Hardware Interface
Figure 10-63. CS Signal Selection
10.6.4.1.2 Byte-Select Signals (BxTx)
BRx[MS] of the accessed memory bank selects a UPM on the currently requested cycle.
The selected UPM affects only the assertion and negation of the appropriate BS signal; its
timing as speciÞed in the RAM word. The BS signals are controlled by the port size of the
accessed bank, the transfer size of the transaction, and the address accessed. Figure 10-64
shows how UPMs control BS signals.
Figure 10-64. BS Signal Selection
The uppermost byte select (BS0) indicates that D[0Ð7] contains valid data during a cycle.
Likewise, BS1 indicates that D[8Ð15] contains valid data, BS2 indicates that D[16Ð23]
contains valid data, and BS3 indicates that D[24Ð31] contains valid data during a cycle, and
so forth. Table 10-31 shows how BS signals affect 64-, 32-, 16-, and 8-bit accesses. Note
that for a refresh timer request, all the BS signals are asserted/negated by the UPM.
UPMA/B/C
SDRAM
GPCM
MUX
MS[0–1] in BRx
CS3
CS4
CS5
CS6
CS7
CS8
Switch
Bank Selected
CS9
CS10
CS11
CS0
CS1
CS2
UPMA
MUX
MS/BUS_SEL
BS0
BS1
BS2
BS3
Bank Selected
PS[0–1] in BRx
A[29–31]
TSIZ
Byte-Select
Logic
UPMB
UPMC
BS4
BS5
BS6
BS7