11 mcc buffer descriptors, 1 receive buffer descriptor (rxbd), Mcc buffer descriptors -21 – Motorola MPC8260 User Manual
Page 751: Receive buffer descriptor (rxbd) -21, Mcc receive buffer descriptor (rxbd) -21, Rxbd field descriptions -21
MOTOROLA
Chapter 27. Multi-Channel Controllers (MCCs)
27-21
Part IV. Communications Processor Module
27.11 MCC Buffer Descriptors
Each MCC channel requires two BD tables (one for transmit and one for receive). Each BD
contains key information about the buffer it deÞnes. The BDs are accessed by the MCC as
needed; BDs can be added dynamically to the BDs chain. The RxBDs chain must include
at least two BDs; the TxBD chain must include at least one BDs.
The MCC BDs are located in the external memory.
27.11.1 Receive Buffer Descriptor (RxBD)
Figure 27-15 shows the RxBD.
RxBD Þelds are described in Table 27-15.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Offset + 0
E
Ñ
W
I
L
F
CM
Ñ
UB
Ñ
LG
NO
AB
CR
Ñ
Offset + 2
Data Length
Offset + 4
Rx Data Buffer Pointer
Offset + 6
Figure 27-15. MCC Receive Buffer Descriptor (RxBD)
Table 27-15. RxBD Field Descriptions
Bits
Name
Description
0
E
Empty
0 The data buffer associated with this BD has been Þlled with received data, or data reception has
been aborted due to an error condition. The user is free to examine or write to any Þelds of this
RxBD. The CP does not use this BD again while the empty bit remains zero.
1 The data buffer associated with this BD is empty, or reception is in progress. This RxBD and its
associated receive buffer are in use by the CP. When E = 1, the user should not write any Þelds of
this RxBD.
1
Ñ
Reserved, should be cleared.
2
W
Wrap (Þnal BD in table)
0 This is not the last BD in the RxBD table.
1 This is the last BD in the RxBD table. After this buffer has been used, the CP receives incoming
data into the Þrst BD in the table (the BD pointed to by RBASE). The number of RxBDs in this
table is programmable and is determined by the wrap bit.
3
I
Interrupt
0 The RXB bit is not set after this buffer has been used, but RXF operation remains unaffected.
1 The RXB or RXF bit in the HDLC interrupt circular table entry is set when this buffer has been
used by the HDLC controller. These two bits may cause interrupts (if enabled).
4
L
Last in frame (only for HDLC mode of operation). The HDLC controller sets L = 1, when this buffer is
the last in a frame. This implies the reception either of a closing ßag or of an error, in which case one
or more of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame
octets to the data length Þeld.
0 This buffer is not the last in a frame.
1 This buffer is the last in a frame.