Motorola MPC8260 - Manual (Page 239)

MOTOROLA Chapter 8. The 60x Bus 8-7
Part III. The Hardware Interface
8.3.2 Address Pipelining and Split-Bus Transactions
The 60x bus protocol provides independent address and data bus capability to support
pipelined and split-bus transaction system organizations. Address pipelining allows the
next address tenure to begin before the current data tenure has Þnished. Although this
ability does not inherently reduce memory latency, support for address pipelining and split-
bus transactions can greatly improve effective bus/memory throughput. These beneÞts are
most fully realized in shared-memory, multiple-master implementations where bus
bandwidth is critical to system performance.
External arbitration (as provided by the MPC8260) is required in systems in which multiple
devices share the system bus. The MPC8260 uses the address acknowledge (AACK) signal
to control pipelining. The MPC8260 supports both one- and zero-level bus pipelining. One-
level pipelining is achieved by asserting AACK to the current address bus master and
granting mastership of the address bus to the next requesting master before the current data
bus tenure has completed. Two address tenures can occur before the current data bus tenure
completes. The MPC8260 also supports non-pipelined accesses.
8.4 Address Tenure Operations
This section describes the three phases of the address tenureÑaddress bus arbitration,
address transfer, and address termination.
8.4.1 Address Arbitration
Bus arbitration can be handled either by an external arbiter or by the internal on-chip
arbiter. The arbitration conÞguration (external or internal) is chosen at system reset. For
internal arbitration, the MPC8260 provides arbitration for the 60x address bus and the
system is optimized for three external bus masters besides the MPC8260. The bus request
(BR) for the external device is an external input to the arbiter. The bus grant signal for the
external device (BG) is output to the external device.The BG signal asserted by MPC8260Õs
on-chip arbiter is asserted one clock after the current master on the bus has asserted AACK;
therefore, it can be called a qualiÞed BG. Assuming that all potential masters negate ABB
one clock after receiving AACK, the device receiving BG can start the address tenure (by
asserting TS) one clock after receiving BG. In addition to the external signals, there are
internal request and grant signals for the MPC8260 processor, communications processor,
refresh controller, and the PCI internal bridge. Bus accesses are prioritized, with
programmable priority. When a MPC8260Õs internal master needs the 60x bus, it asserts the
internal bus request along with the request level. The arbiter asserts the internal bus grant
for the highest priority request.
The MPC8260 supports address bus parking through the use of the parked master bits in
the arbiter conÞguration register. The MPC8260 parks the address bus (asserts the address
bus grant signal in anticipation of an address bus request) to the external master or internal
masters. When a device is parked, the arbiter can hold BG asserted for a device even if that
device has not requested the bus. Therefore, when the parked device needs to perform a bus