Motorola MPC8260 - Manual (Page 436)

13-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
13.3.3 PowerPC Core Interface
The CP communicates with the PowerPC core in several ways:
¥ Many parameters are exchanged through the dual-port RAM.
¥ The CP can execute special commands issued by the core. These commands should
only be issued in special situations like exceptions or error recovery.
¥ The CP generates interrupts through the SIU interrupt controller.
¥ The PowerPC core can read the CPM status/event registers at any time.
13.3.4 Peripheral Interface
The CP uses the peripheral bus to communicate with all of its peripherals. Each FCC and
each SCC has a separate receive and transmit FIFOs. The FCC FIFOs are 192 bytes. The
SCC FIFOs are 32 bytes. The SMCs, SPI, and I
2 C are all double-buffered, creating effective
FIFO sizes of two characters.
Table 13-2 shows the order in which the CP handles requests from peripherals from highest
to lowest priority.
Table 13-2. Peripheral Prioritization
Priority Request
1 Reset in the CPCR or SRESET
2 SDMA bus error
3 Commands issued to the CPCR
4 Emergency (from FCCs, MCCs, and SCCs)
5 IDMA[1Ð4] emulation (defaultÑoption 1) 1
6 FCC1 receive
7 FCC1 transmit
8 MCC1 receive
9 MCC2 receive
10 MCC1 transmit
11 MCC2 transmit
12 FCC2 receive
13 FCC2 transmit
14 FCC3 receive
15 FCC3 transmit
16 SCC1 receive
17 SCC1 transmit
18 SCC2 receive