Motorola MPC8260 - Manual (Page 122)

3-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
10030 PPC_ALRL 60x bus arbitration-level register low
(next 8 clients) 32 bits 4.3.2.3/4-28
10034 LCL_ACR Local arbiter conÞguration register 8 bits 4.3.2.4/4-29
10038 LCL_ALRH Local arbitration-level register (Þrst 8
clients) 32 bits 4.3.2.5/4-30
1003C LCL_ALRL Local arbitration-level register (next 8
clients) 32 bits 4.3.2.3/4-28
10040 TESCR1 60x bus transfer error status control
register 1 32 bits 4.3.2.10/4-36
10044 TESCR2 60x bus transfer error status control
register 2 32 bits 4.3.2.11/4-37
10048 L_TESCR1 Local bus transfer error status control
register 1 32 bits 4.3.2.12/4-38
1004C L_TESCR2 Local bus transfer error status control
register 2 32 bits 4.3.2.13/4-39
10050 PDTEA 60x bus DMA transfer error address 32 bits 18.2.3/18-4
10054 PDTEM 60x bus DMA transfer error MSNUM 8 bits 18.2.4/18-4
10055 Reserved Ñ 24 bits Ñ
10058 LDTEA Local bus DMA transfer error address 32 bits 18.2.3/18-4
1005C LDTEM Local bus DMA transfer error MSNUM 8 bits 18.2.4/18-4
1005DÐ100FF Reserved Ñ 163 bytes Ñ
Memory Controller
10100 BR0 Base register bank 0 32 bits 10.3.1/10-14
10104 OR0 Option register bank 0 32 bits 10.3.2/10-16
10108 BR1 Base register bank 1 32 bits 10.3.1/10-14
1010C OR1 Option register bank 1 32 bits 10.3.2/10-16
10110 BR2 Base register bank 2 32 bits 10.3.1/10-14
10114 OR2 Option register bank 2 32 bits 10.3.2/10-16
10118 BR3 Base register bank 3 32 bits 10.3.1/10-14
1011C OR3 Option register bank 3 32 bits 10.3.2/10-16
10120 BR4 Base register bank 4 32 bits 10.3.1/10-14
10124 OR4 Option register bank 4 32 bits 10.3.2/10-16
10128 BR5 Base register bank 5 32 bits 10.3.1/10-14
1012C OR5 Option register bank 5 32 bits 10.3.2/10-16
10130 BR6 Base register bank 6 32 bits 10.3.1/10-14
Table 3-1. Internal Memory Map (Continued)
Internal
Address
Abbreviation Name Size Section/Page Number