Motorola MPC8260 - Manual (Page 465)

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-11
Part IV. Communications Processor Module
Table 14-1. SI x RAM Entry (MCC = 0)
Bits Name Description
0 MCC The entry controls the functionality of the other bits in the SI x RAM entry.
0 The entry refers to other serial controllers (FCCs, SCCs, SMC, according to the CSEL Þeld).
1 The entry refers to the MCC.
1 SWTR Switch Tx and Rx. Valid only in the receive route RAM and ignored in the transmit route RAM. SWTR
affects the operation of both L1RXD and L1TXD. SWTR is set only in special situations where the
user prefers to receive data from a transmit pin and transmit data on a receive pin. For instance,
where devices A and B are connected to the same TDM, each with different time-slots. Normally,
there is no opportunity for stations A and B to communicate with each other directly over the TDM,
because they both receive the same TDM receive data and transmit on the same TDM transmit
signal.
0 Normal operation of L1TXD and L1RXD.
1 Data for this entry is sent on L1RXD and received from L1TXD.
See Figure 14-8 for details.
2Ð5 SSELx Strobe select. There are four strobes available that can be assigned to the receive RAM and
asserted/negated with the received clock of this TDM channel (L1RCLKx). They can also be assigned
to the transmit RAM and asserted/negated with the transmit clock of this TDM channel (L1TCLKx).
Each bit corresponds to the value the strobe should have during this bit/byte group. There are four
strobe pins for all eight strobe bits in the SI
x RAM entries, so the value on a strobe pin is the logical
OR of the Rx and Tx RAM entry strobe bit.s Multiple strobes can be asserted simultaneously. A
strobe conÞgured to be asserted in consecutive SI
x RAM entries remains continuously asserted for
both entries. A strobe asserted on the last entry in a table is negated after the last entry is processed.
Note: Each strobe is changed with the corresponding RAM clock and is output only if the
corresponding parallel I/O is conÞgured as a dedicated pin. If a strobe is programmed to be asserted
in more than one set of entries (the SI route entries for more then one TDM channel select the same
strobe), the assertion of the strobe corresponds to the logical OR of all possible sources. This use of
strobes is not useful for most applications. A given strobe should be selected in only one set of SI
x
RAM entries.
6 Ñ Reserved, should be cleared.
7Ð10 CSEL Channel select
0000 The bit/byte group is not supported by the MPC8260. The transmit data pin is three-stated and
the receive data pin is ignored.
0001 The bit/byte group is routed to SCC1.
0010 The bit/byte group is routed to SCC2.
0011 The bit/byte group is routed to SCC3.
0100 The bit/byte group is routed to SCC4.
0101 The bit/byte group is routed to SMC1.
0110 The bit/byte group is routed to SMC2.
0111 The bit/byte group is not supported by the MPC8260. This code is also used in SCIT mode as
the D channel grant. See Section 14.7.2.2, ÒSCIT Programming.Ó
1000 Reserved.
1001 The bit/byte group is routed to FCC1.
1010 The bit/byte group is routed to FCC2.
1011 The bit/byte group is routed to FCC3.
11xx Reserved.