Motorola MPC8260 - Manual (Page 207)

MOTOROLA Chapter 6. External Signals 6-5
Part III. The Hardware Interface
IRQ5
DP[5]
TBEN
EXT_DBG3
Interrupt request 5ÑThis input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
60x data parity 5Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 5 pin should give odd parity (odd number of Ô1Õs) on the
group of signals that includes data parity 5 and D[40Ð47].
Time base enableÑThis is a count enable input to the Time Base counter in the core.
External data bus grant 3Ñ(Output) The MPC8260 asserts this pin to grant 60x data bus ownership
to an external bus master.
IRQ6
DP[6]
CSE[0]
Interrupt request 6ÑThis input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
60x data parity 6Ñ(Input/output)The 60x agent that drives the data bus drives also the data parity
signals. The value driven on data parity 6 pin should give odd parity (odd number of Ô1Õs) on the
group of signals that includes data parity 6 and D[48Ð55].
Cache set entry 0ÑThe cache set entry outputs from the core represent the cache replacement set
element for the current core transaction reloading into or writing out of the cache.
IRQ7
DP[7]
CSE[1]
Interrupt request 7ÑThis input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
60x data parity 7Ñ(Input/output)The 60x master or slave that drives the data bus drives also the
data parity signals. The value driven on data parity 7 pin should give odd parity (odd number of Ô1Õs)
on the group of signals that includes data parity 7 and D[56Ð63].
Cache set entry 1ÑThe cache set entry outputs from the core represent the cache replacement set
element for the current core transaction reloading into or writing out of the cache.
PSDVAL 60x data validÑ(Input/output)Assertion of the PSDVAL pin indicates that a data beat is valid on the
data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted to
indicate 60x data transfer terminations while the PSDVAL signal is asserted with each data beat
movement. Thus always when TA is asserted, PSDVAL will be asserted but when PSDVAL is
asserted, TA is not necessarily asserted. For example when a double word (2x64 bits) transfer is
initiated by the SDMA to a memory device that has 32 bits port size, PSDVAL will be asserted 3
times without TA and Þnally both pins will be asserted to terminate the transfer.
TA Transfer acknowledgeÑ(Input/output) Indicates that a 60x data beat is valid on the data bus. For
60x single beat transfers, assertion of this pin indicates the termination of the transfer. For 60x burst
transfers TA is asserted four times to indicate the transfer of four data beats with the last assertion
indicating the termination of the burst transfer.
TEA Transfer error acknowledgeÑ(Input/output)Assertion of this pin indicates a bus error. 60x masters
within the MPC8260 monitor the state of this pin. MPC8260Õs internal bus monitor may assert this
pin in case it identiÞed a 60x bus transfer that is hung.
GBL
IRQ1
GlobalÑ(Input/output)When a 60x master within the chip initiates a bus transaction it drives this
pin. When an external 60x master initiates a bus transaction it should drive this pin. Assertion of this
pin indicates that the transfer is global and it should be snooped by caches in the system. The
MPC8260MPC8260Õs data cache monitors the state of this pin.
Interrupt request 1ÑThis input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
CI
BADDR29
IRQ2
Cache inhibitÑOutput pin. Used for L2 cache control. For each MPC8260 60x transaction initiated
in the core, the state of this pin indicates if this transaction should be cached or not. Assertion of the
CI pin indicates that the transaction should not be cached.
Burst address 29ÑThere are Þve burst address output pins. These pins are outputs of the 60x
memory controller. These pins are used in external master conÞguration and are connected directly
to memory devices controlled by MPC8260Õs memory controller.
Interrupt request 2ÑThis input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core.
Table 6-1. External Signals (Continued)
Signal Description