Motorola MPC8260 - Manual (Page 545)

MOTOROLA Chapter 18. SDMA Channels and IDMA Emulation 18-21
Part IV. Communications Processor Module
Table 18-7 describes valid STS/DTS values for memory-to-memory operations.
Table 18-8 describes valid STS/DTS values for memory/peripheral operations.
Table 18-7. Valid Memory-to-Memory STS/DTS Values
DMA_WRAP
Internal
Buffer
Size
SS_MAX STS (in Bytes) DTS (in Bytes)
Number of Transfers to
Fill Internal Buffer
STS Size DTS Size
000 64 1 * 32
1 * 32 32 1 1
32 1 * 32 1 1
001 128 3 * 32
3 * 32 3 * 32, 32 1 1, 3
3 * 32, 32 3 * 32 1, 3 1
010 256 7 * 32
7 * 32 7 * 32, 32 1 1, 7
7 * 32, 32 7 * 32 1, 7 1
011 512 15 * 32
15 * 32 15 * 32, 3 * 32, 5 * 32, 32 1 1, 5, 3, 15
15 * 32, 3 * 32, 5 * 32, 32 15 * 32 1, 5, 3, 15 1
100 1024 31 * 32
31 * 32 31 * 32, 32 1 1, 31
31 * 32, 32 31 * 32 1, 31 1
101 2048 63 * 32
63 * 32 63 * 32, 9 * 32, 7 * 32, 32 1 1, 7, 9, 63
63 * 32, 9 * 32, 7 * 32, 32 63 * 32 1, 7, 9, 63 1
Table 18-8. Valid STS/DTS Values for Peripherals
DMA_WRAP Internal Buffer Size SS_MAX S/D Mode STS (in Bytes) DTS (in Bytes)
000 64 1 * 32 01 1 * 32 1, 2, 4, 8 (single) 1 ; 32
(burst) 2
10 1, 2, 4, 8 (single); 32
(burst)
1 * 32
001 128 3 * 32 01 3 * 32 1, 2, 4, 8 (single); 32
(burst)
10 1, 2, 4, 8 (single); 32
(burst)
3 * 32
010 256 7 * 32 01 7 * 32 1, 2, 4, 8 (single); 32
(burst)
10 1, 2, 4, 8 (single); 32
(burst)
7 * 32