Motorola MPC8260 User Manual

Page 686

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24-18

MPC8260 PowerQUICC II UserÕs Manual

MOTOROLA

Part IV. Communications Processor Module

Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer
Descriptors (BDs).
Ó Data length includes the total number of frame octets (including four
bytes for CRC).

Figure 24-7 shows an example of how RxBDs are used in receiving.

4

L

Last in frame. The Ethernet controller sets this bit when this buffer is the last one in a frame, which
occurs when the end of a frame is reached or an error is received. In the case of error, one or more of
the CL, OV, CR, SH, NO, and LG bits are set. The Ethernet controller writes the number of frame octets
to the data length Þeld.
0 The buffer is not the last one in a frame.
1 The buffer is the last one in a frame.

5

F

First in frame. The Ethernet controller sets this bit when this buffer is the Þrst one in a frame.
0 The buffer is not the Þrst one in a frame.
1 The buffer is the Þrst one in a frame.

6

Ñ

Reserved, should be cleared.

7

M

Miss. (valid only if L = 1) The Ethernet controller sets M for frames that are accepted in promiscuous
mode, but are ßagged as a miss by internal address recognition. Thus, in promiscuous mode, M
determines whether a frame is destined for this station.
0 The frame is received because of an address recognition hit.
1 The frame is received because of promiscuous mode.

8Р9

С

Reserved, should be cleared.

10

LG

Rx frame length violation. Set when a frame length greater than the maximum deÞned for this channel
has been recognized. Only the maximum number of bytes allowed is written to the buffer.

11

NO

Rx nonoctet-aligned frame. Set when a frame containing a number of bits not divisible by eight is
received. Also, the CRC check that occurs at the preceding byte boundary generated an error.

12

SH

Short frame. Set if a frame smaller than the minimum deÞned for this channel was recognized. Occurs
if PSMR[RSH] = 1.

13

CR

Rx CRC error. set when a frame contains a CRC error.

14

OV

Overrun. Set when a receiver overrun occurs during frame reception.

15

CL

Collision. This frame is closed because a collision occurred during frame reception. CL is set only if a
late collision occurs or if PSMR[RSH] is enabled. Late collisions are better deÞned in PSMR[LCW].

Table 24-7. SCC Ethernet Receive RxBD Status and Control

Field Descriptions (Continued)

Bits Name

Description

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